AND8139 Datasheet, PDF (2/2 Pages) ON Semiconductor – Ultra-Low Voltage MiniGate Devices Solve 1.2 V Interface Problems

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It should be noticed that the signal is inverted for the case
of the transistor. This may or may not be desirable. In fact,
the phase inversion would be the only plausible reason to
prefer the transistor case over the passive resistor divider.
The last option that will be presented will be the
ON Semiconductor sub−one volt family, NL17SVxx
products. We have the choice of inverted or non−inverted
output. Since the devices are Over−Voltage Tolerant (OVT)
at their inputs, the designer may simply apply the 3.3 V
signal to the input of the device. For this application,
Figure 3 shows the supply voltage to the device will be 1.2
V. This assures that the output will be logic level compatible
with the device that it is driving.
3.3 V
0
1.2 V
NL17SV16XV5T2
Figure 3.
Since the 3.3 V logic is only driving a capacitive input,
there is very little power dissipation at the input. To calculate
the total power consumed, we must use a different equation
that depends on the Power Dissipation Capacitance (C_PD) as
the main factor. To calculate the power loss in the gate, the
following formula is used:
PD + (CPD @ VCC2 @ f) ) (ICC @ VCC)
At 35 MHz and C_PD of 20 pf, the equation works out to
~ 2.0 mW total power, with about 50% of the power
consumed in leakage current and 50% in the switching. The
delay time is only 10 ns (worst case), at V_CC of 1.2 V.
Conclusion
The use of a single gate for logic level translation saves
90% of the power required for a passive solution and even
more compared to a transistor solution. The manufacturer
needs only to place one part versus two or more for any other
approach. The time delay is much faster and less circuit
dependent. Output may be either inverted or non−inverted
(by selecting appropriate single gate device). The circuit
will easily operate past 50 MHz, if needed at 1.2 V. It is clear
that this is the only practical solution for logic level
translation at low power.
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