AND8139 Datasheet, PDF (1/2 Pages) ON Semiconductor – Ultra-Low Voltage MiniGate Devices Solve 1.2 V Interface Problems

AND8139/D
Ultra−Low Voltage
MiniGatet Devices Solve
1.2 V Interface Problems
Prepared by: Fred Zlotnick
ON Semiconductor
http://onsemi.com
APPLICATION NOTE
Many integrated circuits such as microprocessors and
DSPs need to operate at very low voltage in order to
conserve power and not over dissipate. Issues arise when the
designer has a device, like a DSP, operating at 1.2 V and
needs to interface with other semiconductors operating at
3.3 V or more.
When performing the interface between a 3.3 V (or any
voltage between 1.2 V and 3.3 V) the one single answer that
solves all problems, simply with a minimum of board space,
is the NL17SVyyyXV5T2 family. With the six available
devices, the signal can be applied to the input and brought
to the DSP in the fastest possible time (minimum delay),
while occupying minimum board space and consuming
minimum power.
The designer might ask why not simply use resistors to
perform voltage division? Resistors can certainly be used for
some applications but they consume power and limit the
operating frequency and create a delay (when the designer
includes the C of the input device). Figure 1 illustrates the
use of two resistors to limit the voltage on the DSP. For
simplicity, this article will not take into account tolerance
issues. That will be left to the reader if he chooses this
approach. In all cases, we will use V₁ = 3.3 V, V₂ = 1.2 V,
f = 35 MHz, and C_IN = 10 pf. If 640 Ω and 330 Ω resistors
3.3 V
R1
1.2 V
R2
are used, the circuit will perform the required voltage
division. The loading will be 330 Ω and draw 1.0 mA when
the device is on. If it is assumed to be a 50% duty cycle, then
the power consumption for the simple resistor divider will
be 16 mW. This power consumption is so high that it would
be ruled out immediately. If we would have used larger value
resistors, the frequency response would be impaired and
35 MHz would be impossible. The delay time through this
circuit will be about 15 to 20 ns.
A second possible scheme might be to use a transistor. If
an NPN transistor were used, it would need a voltage
division scheme similar to Figure 1 and the values would
need to be the same in order to keep the frequency response
to > 50 MHz f_3dB. Power dissipation would be actually
higher than for the passive case because we would have a
third resistor from 1.2 V to the collector (Figure 2). We
would have another 5.0 mW of power dissipation due to the
output resistor. This solution would consume > 20 mW of
power and again is outrageously high in the power budget.
In addition, the manufacturer would have to place three parts
(three resistors and one transistor or one BRT plus one
resistor). Delay time would be longer than the passive
solution above, hence more costly and would present
absolutely no advantage over the simple resistive divider.
3.3 V
640
220
1.2 V
220
1.2 V
Figure 1.
Figure 2.
© Semiconductor Components Industries, LLC, 2003
1
December, 2003 − Rev. 0
Publication Order Number:
AND8139/D