LC87F7NJ2A Datasheet, PDF (19/28 Pages) ON Semiconductor – 8-bit Microcontroller

LC87F7NJ2A
Serial I/O Characteristics at Ta = 40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V, 0.190μs  tCYC  200μs
SIO0 Serial I/O Characteristics (Note 4-1-1) at VDD = 2.7 V to 3.6V 0.190μs  tCYC  200μs
Parameter
Frequency
Symbol
tSCK(1)
Pin/Remarks
Conditions
SCK0(P12)
See Fig. 6.
Specification
VDD [V]
min
typ
max
unit
2
Low level
pulse width
High level
pulse width
tSCKL(1)
tSCKH(1)
tSCKHA(1)
Frequency
tSCK(2)
SCK0(P12)
Low level
pulse width
High level
pulse width
tSCKL(2)
tSCKH(2)
tSCKHA(2)
Data setup time tsDI(1)
Data hold time
thDI(1)
SB0(P11),
SI0(P11)
• Continuous data
transmission/reception mode
• See Fig. 6.
(Note 4-1-2)
• CMOS output selected
• See Fig. 6.
• Continuous data
transmission/reception mode
• CMOS output selected
• See Fig. 6.
• Must be specified with
respect to rising edge of
SIOCLK.
• See Fig. 6.
1
2.5 to 3.6
1
4
tCYC
4/3
1/2
tSCK
2.5 to 3.6
1/2
tSCKH(2)
+2tCYC
tSCKH(2)
+(10/3)
tCYC
tCYC
0.03
2.5 to 3.6
0.03
Output
delay time
tdD0(1)
tdD0(2)
tdD0(3)
SO0(P10),
SB0(P11)
• Continuous data
transmission/reception mode
(Note 4-1-3)
• Synchronous 8-bit mode
(Note 4-1-3)
(Note 4-1-3)
2.5 to 3.6
(1/3)tCYC
+0.05
s
1tCYC
+0.05
(1/3)tCYC
+0.05
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is
"H" to the first negative edge of the serial clock must be longer than tSCKHA.
Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of
output state change in open drain output mode. See Fig. 6.
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