CS51312 Datasheet, PDF (18/22 Pages) Cherry Semiconductor Corporation – Synchronous CPU Buck Controller for 12V Only Applications

CS51312
Step 8: Control IC Power Dissipation
The power dissipation of the IC varies with the MOSFETs
used, V_CC, and the CS51312 operating frequency. The
average MOSFET gate charge current typically dominates
the control IC power dissipation.
The IC power dissipation is determined by the formula:
PCONTROLIC + ICC1VCC1 ) PGATE(H) ) PGATE(L)
where:
P_CONTROLIC = control IC power dissipation;
I_CC1 = IC quiescent supply current;
V_CC1 = IC supply voltage;
P_GATE(H) = upper MOSFET gate driver (IC) losses;
P_GATE(L) = lower MOSFET gate driver (IC) losses.
The upper (switching) MOSFET gate driver (IC) losses
are:
PGATE(H) + QGATE(H) FSW VGATE(H)
where:
P_GATE(H) = upper MOSFET gate driver (IC) losses;
Q_GATE(H) = total upper MOSFET gate charge;
F_SW = switching frequency;
V_GATE(H) = upper MOSFET gate voltage.
The lower (synchronous) MOSFET gate driver (IC)
losses are:
PGATE(L) + QGATE(L) FSW VGATE(L)
where:
P_GATE(L) = lower MOSFET gate driver (IC) losses;
Q_GATE(L) = total lower MOSFET gate charge;
F_SW = switching frequency;
V_GATE(L) = lower MOSFET gate voltage.
The junction temperature of the control IC is primarily a
function of the PCB layout, since most of the heat is removed
through the traces connected to the pins of the IC.
Step 9: Slope Compensation
Voltage regulators for today’s advanced processors are
expected to meet very stringent load transient requirements.
One of the key factors in achieving tight dynamic voltage
regulation is low ESR at the CPU input supply pins. Low
ESR at the regulator output results in low output voltage
ripple. The consequence is, however, that there’s very little
voltage ramp at the control IC feedback pin (V_FB) and
regulator sensitivity to noise and loop instability are two
undesirable effects that can surface. The performance of the
CS51312−based CPU V_CC(CORE) regulator is improved
when a fixed amount of slope compensation is added to the
output of the PWM Error Amplifier (COMP pin) during the
regulator Off−Time. Referring to Figure 14, the amount of
voltage ramp at the COMP pin is dependent on the gate
voltage of the lower (synchronous) FET and the value of
resistor divider formed by R1and R2.
ǒ Ǔ VSLOPECOMP + VGATE(L)
R2
R1 ) R2
ǒ_{1.0 * e} ^*t ^tǓ
where:
V_SLOPECOMP = amount of slope added;
V_GATE(L) = lower MOSFET gate voltage;
R1, R2 = voltage divider resistors;
t = t_OFF (switch off−time);
τ = RC constant determined by C1 and the parallel
combination of R1, R2 (Figure 14), neglecting the low
driver output impedance.
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