CS51312 Datasheet, PDF (11/22 Pages) Cherry Semiconductor Corporation – Synchronous CPU Buck Controller for 12V Only Applications

CS51312
Channel 1 − Regulator Input Voltage and V_CC1 (10 V/div)
Channel 2 − COMP (2.0 V/div)
Channel 3 − Regulator Output Voltage (1.0 V/div)
Figure 10. Normal Startup (5.0 ms/div)
Channel 1 − V_CC2 (10 V/div)
Channel 2 − GATE(H) (10 V/div)
Channel 3 − Inductor Switching Node (10 V/div)
Channel 4 − Regulator Output Voltage (2.0 V/div)
Figure 11. Normal Startup Showing Initial Pulse
Followed by Soft Start (5.0 ms/div)
If the voltage across the Current Sense resistor generates
a voltage difference between the V_FB and V_OUT pins that
exceeds the OVC Comparator Offset Voltage (86 mV
typical), the Fault latch is set. This causes the COMP pin to
be quickly discharged, turning off GATE(H) and the upper
NFET since the voltage on the COMP pin is now less than
the 1.1 V PWM comparator offset. The Fault latch is reset
when the voltage on the COMP decreases below the
discharge threshold voltage (0.25 V typical). The COMP
capacitor will again begin to charge, and when it exceeds the
1.1 V PWM comparator offset, the regulator output will Soft
Start normally (see Figure 12).
Channel 1 − Regulator Output Voltage (1.0 V/div)
Channel 2 − COMP Pin (1.0 V/div)
Channel 3 − V_CC (10 V/div)
Figure 12. Startup with COMP Pre−Charged to
2.0 V (2.0 ms/div)
When driving large capacitive loads, the COMP must
charge slowly enough to avoid tripping the CS51312
overcurrent protection. The following equation can be used
to ensure unconditional startup:
ICHG
CCOMP
t
ILIM * ILOAD
COUT
where:
I_CHG = COMP Source Current (30 μA typical);
C_COMP = COMP Capacitor value (0.1 μF typical);
I_LIM = Current Limit Threshold;
I_LOAD = Load Current during startup;
C_OUT = Total Output Capacitance.
Normal Operation
During normal operation, Switch Off−Time is constant
and set by the C_OFF capacitor. Switch On−Time is adjusted
by the V² Control loop to maintain regulation. This results
in changes in regulator switching frequency, duty cycle, and
output ripple in response to changes in load and line. Output
voltage ripple will be determined by inductor ripple current
and the ESR of the output capacitors
Transient Response
The CS51312 V² Control Loop’s 200 ns reaction time
provides unprecedented transient response to changes in
input voltage or output current. Pulse−by−pulse adjustment
of duty cycle is provided to quickly ramp the inductor
current to the required level. Since the inductor current
cannot be changed instantaneously, regulation is maintained
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