AX8052F143_17 Datasheet, PDF (18/45 Pages) ON Semiconductor – SoC Ultra-Low Power RF-Microcontroller

AX8052F143
CIRCUIT DESCRIPTION
The AX8052F143 is a true single chip narrow−band,
ultra−low power RF−microcontroller SoC for use in
licensed and unlicensed bands ranging from 70 MHz to
1050 MHz. The on−chip transceiver consists of a fully
integrated RF front−end with modulator and demodulator.
Base band data processing is implemented in an advanced
and flexible communication controller that enables user
friendly communication.
The AX8052F143 contains a high speed microcontroller
compatible to the industry standard 8052 instruction set. It
contains 64 kBytes of FLASH and 8.25 kBytes of internal
SRAM.
The AX8052F143 features 3 16−bit general purpose
timers with SD capability, 2 output compare units for
generating PWM signals, 2 input compare units to record
timings of external signals, 2 16−bit wakeup timers, a
watchdog timer, 2 UARTs, a Master/Slave SPI controller, a
10−bit 500 kSample/s A/D converter, 2 analog comparators,
a temperature sensor, a 2 channel DMA controller, and a
dedicated AES crypto controller. Debugging is aided by a
dedicated hardware debug interface controller that connects
using a 3−wire protocol (1 dedicated wire, 2 shared with
GPIO) to the PC hosting the debug software.
While the radio carrier/LO synthesizer can only be
clocked by the crystal oscillator (carrier stability
requirements dictate a high stability reference clock in the
MHz range), the microcontroller and its peripherals provide
extremely flexible clocking options. The system clock that
clocks the microcontroller, as well as peripheral clocks, can
be selected from one of the following clock sources: the
crystal oscillator, an internal high speed 20MHz oscillator,
an internal low speed 640 Hz/10 kHz oscillator, or the low
frequency crystal oscillator. Prescalers offer additional
flexibility with their programmable divide by a power of two
capability. To improve the accuracy of the internal
oscillators, both oscillators may be slaved to the crystal
oscillator.
AX8052F143 can be operated from a 1.8 V to 3.6 V power
supply over a temperature range of –40°C to 85°C, it
consumes 4 − 51 mA for transmitting, depending on the
output power, 6.8 – 11 mA for receiving.
The AX8052F143 features make it an ideal interface for
integration into various battery powered solutions such as
ticketing or as transceiver for telemetric applications e.g. in
sensors. As primary application, the transceiver is intended
for UHF radio equipment in accordance with the European
Telecommunication Standard Institute (ETSI) specification
EN 300 220−1 and the US Federal Communications
Commission (FCC) standard Title 47 CFR part 15 as well as
Part 90. Additionally AX8052F143 is suited for systems
targeting compliance with Wireless M−Bus standard EN
13757−4:2005. Wireless M−Bus frame support (S, T, R) is
built−in.
The AX8052F143 sends and receives data in frames. This
standard operation mode is called Frame Mode. Pre and post
ambles as well as checksums can be generated
automatically.
AX8052F143 supports any data rate from 0.1 kbps to
125 kbps for FSK, MSK, 4−FSK, GFSK, GMSK and ASK
modulations. To achieve optimum performance for specific
data rates and modulation schemes several register settings
to configure the AX8052F143 are necessary, they are
outlined in the following, for details see the AXSEM
RadioLab software which calculates the necessary register
settings and the AX5043 Programming Manual.
The receiver supports multi−channel operation for all data
rates and modulation schemes.
Microcontroller
The AX8052 microcontroller core executes the industry
standard 8052 instruction set. Unlike the original 8052,
many instructions are executed in a single cycle. The system
clock and thus the instruction rate can be programmed freely
from DC to 20 MHz.
Memory Architecture
The AX8052F143 Microcontroller features the highest
bandwidth memory architecture of its class. Figure 6 shows
the memory architecture. Three bus masters may initiate bus
cycles:
• The AX8052 Microcontroller Core
• The Direct Memory Access (DMA) Engine
• The Advanced Encryption Standard (AES) Engine
Bus targets include:
• Two individual 4 kBytes RAM blocks located in X
address space, which can be simultaneously accessed
and individually shut down or retained during sleep
mode
• A 256 Byte RAM located in internal address space,
which is always retained during sleep mode
• A 64 kBytes FLASH memory located in code space.
• Special Function Registers (SFR) located in internal
address space accessible using direct address mode
instructions
• Additional Registers located in X address space
(X Registers)
The upper half of the FLASH memory may also be
accessed through the X address space. This simplifies and
makes the software more efficient by reducing the need for
generic pointers.
NOTE: Generic pointers include, in addition to the
address, an address space tag.
SFR Registers are also accessible through X address
space, enabling indirect access to SFR registers. This allows
driver code for multiple identical peripherals (such as
UARTs or Timers) to be shared.
The 4 word × 16 bit fully associative cache and a pre−fetch
controller hide the latency of the FLASH.
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