NCP1615_16 Datasheet, PDF(17/46 Page) ON Semiconductor – High Voltage High Efficiency Power Factor Correction Controller

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NCP1615_16 Datasheet, PDF (17/46 Pages) ON Semiconductor – High Voltage High Efficiency Power Factor Correction Controller

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NCP1615

ON TIME MODULATION

Letâs analyze the ac line current absorbed by the PFC

boost stage. The initial inductor current at the beginning of

each switching cycle is always zero. The coil current ramps

up when the MOSFET is on. The slope is (Vin/L) where L

is the coil inductance. At the end of the on time period (t1),

the inductor starts to demagnetize. The inductor current

ramps down until it reaches zero. The duration of this phase

is (t2). In some cases, the system enters then the deadâtime

(t3) that lasts until the next clock is generated.

One can show that the ac line current is given by:

Æª Æ« t1Çt1 ) t2Ç

Iin + Vin

2TL

(eq. 2)

Where T = (t1 + t2 + t3) is the switching period and Vin is the

ac line rectified voltage.

In light of this equation, we immediately note that Iin is

proportional to Vin if [t1*(t1 + t2)/T] is a constant.

Figure 9. PFC Boost Converter (left) and Inductor Current in DCM (right)

The NCP1615 operates in voltage mode. As portrayed by

Figure 10, t1 is controlled by the signal VTON generated by

the regulation block and an internal ramp as follows:

Cramp @ VTON

Ich

(eq. 3)

The charge current is constant at a given input voltage (as

mentioned, it is four times higher at high line compared to

its value at low line). Cramp is an internal timing capacitor.

The output of the regulation block, VControl, is linearly

transformed into the signal VREGUL varying between 0 and

1.5 V. VREGUL is the voltage that is injected into the PWM

section to modulate the MOSFET duty ratio. The NCP1615

includes circuitry that processes VREGUL to generate the

VTON signal that is used in the PWM section (see Figure 11).

It is modulated in response to the deadtime sensed during the

precedent current cycles, that is, for a proper shaping of the

ac line current. This modulation leads to:

VTON

@ VREGUL

t1 ) t2

(eq. 4)

Çt1 ) t2Ç

VTON @

+ VREGUL

Given the low regulation bandwidth of the PFC systems,

VControl and thus VREGUL are slow varying signals. Hence,

the (Vton*(t1 + t2)/T) term is substantially constant.

Provided that during t1 it is proportional to VTON,

Equation 2 leads to:

Iin + k @ Vin,

where k is a constant.

Æª Æ« k + constant +

VREGUL

VREGUL(MAX)

ton(MAX)

Where ton(MAX) is the maximum on time obtained when

VREGUL is at its maximum level, VREGUL(MAX). The

parametric table shows that ton(MAX) is equal to 25 ms

(tON(LL)) at low line and to 6.3 ms (ton(HL)) at high line.

Hence, we can rewrite the above equation as follows:

Iin

Vin @ ton(LL)

2@L

VREGUL

VREGUL(MAX)

at low line.

Iin

Vin

ton(HL)

VREGUL

VREGUL(MAX)

From these equations, we can deduce the expression of the

average input power at low line as shown below:

Vin,rms 2 @ ton(LL) @ VREGUL

Pin(ave) +

2 @ L @ VREGUL(MAX)

The input power at high line is shown below:

Vin,rms 2 @ ton(HL) @ VREGUL

Pin(ave) +

2 @ L @ VREGUL(MAX)

Hence, the maximum power that can be delivered by the

PFC stage at low line is given by equation below:

Vin,rms 2 @ ton(LL)

Pin(MAX) +

2@L

The maximum power at high line is given by the equation

below:

Vin,rms 2 @ ton(HL)

Pin(MAX) +

2@L

The input current is then proportional to the input voltage

resulting in a properly shaped ac line current.

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