CYIL2SM1300-EVAL Datasheet, PDF (17/41 Pages) ON Semiconductor – LUPA 1300-2: High Speed CMOS Image Sensor

CYIL2SM1300AA
Res_length (76 and 77). This register sets the length of the
internal pixel array reset (how long are all pixel reset
simultaneously). This value is expressed in 'number of lines' or
in clock cycles (depends on seqmode3[6]).
Res_dsts_length. This register sets the length of the internal
dual and triple slope reset pulses when enabled. This value is
expressed in 'number of lines' or in clock cycles (depends on
seqmode3[6]).
Tint_timer (79 and 80). This register sets the length of the
integration time. This value is expressed in 'number of lines' or
in clock cycles (depends on seqmode3[6]).
Tint_ds_timer (81 and 82). This register sets the length of the
dual slope integration time. This value is expressed in 'number
of lines' or in clock cycles (depends on seqmode3[6]).
Tint_ts_timer (83 and 84). This register sets the length of the
triple slope integration time. This value is expressed in 'number
of lines' or in clock cycles (depends on seqmode3[6]).
Data Interface (SPI)
The serial 4-wire interface (or Serial to Parallel Interface) uses a
serial input or output to shift the data in or out the register buffer.
The chip's configuration registers are accessed from the outside
world through the SPI protocol. A 4-wire bus runs over the chip
and connects the SPI I/Os with the internal register blocks.
The interface consists of:
■ cs_n: chip select, when LOW the chip is selected
■ clk: the spi clock
■ in: Master out, Slave in, the serial input of the register
■ out: Master in, Slave out, the serial output of the register
SPI Protocol
The information on the data 'in' line is:
■ A command bit C, indicating a write ('1') or a read ('0') access
■ 7-bit address
■ 8-bit data word (in case of a write access)
The data 'out' line is generally in High Z mode, except when a
read request is performed.
Data is always written on the bus on the falling edge of the clock,
and sampled on the rising edge, as seen in Figure 9 and
Figure 10. This is valid for both the 'in' and 'out' bus. The system
clock must be active to keep the SPI uploads stored on the chip.
The SPI clock speed must be slower by a factor of 30 when
compared to the system clock (315 MHz nominal speed).
Figure 9. Write Access (C='1')
The 'out' line is held to High Z. The data for the address A is transferred from the shift register to the active register bank (that is,
sampled) on a rising edge of cs_n. Only the register block with address A can write its data on the 'out' bus. The data on 'in' is ignored.
Figure 10. Read Access (C='0')
Document Number: 001-24599 Rev. *C
Page 17 of 41
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