NCN49597MNG Datasheet, PDF (16/29 Pages) ON Semiconductor – Power Line Communication Modem

NCN49597
Table 6. CHIP_CLK IN FUNCTION OF SELECTED BAUD RATE AND MAINS FREQUENCY
R_CONF[0]
Mains frequency
R_CONF[2:1]
Baudrate
00b
300 bps
01b
600 bps
0
50 Hz
10b
1200 bps
11b
2400 bps
00b
360 bps
01b
720 bps
1
60 Hz
10b
1440 bps
11b
2880 bps
CHIP_CLK
2400 Hz
4800 Hz
9600 Hz
19200 Hz
2880 Hz
5760 Hz
11520 Hz
23040 Hz
The PLL significantly reduces the clock jitter. This makes
the modem less sensitive to timing variations; as a result, a
cheaper zero crossing detector circuit may be used.
The PLL input is only sensitive to rising edges.
If no zero crossings are detected, the PLL freezes its
internal timers in order to maintain the CHIP_CLK timing.
Figure 14. Using the ZC_ADJUST Register to Compensate for Zero Crossing Delay (example for 50 Hz)
http://onsemi.com
16