LB11923V Datasheet, PDF (16/20 Pages) Sanyo Semicon Device – Three-Phase Brushless Motor Driver

LB11923V
IC Operation Description
1. Speed Control Circuit
This IC implements speed control using the combination of a speed discriminator circuit and a PLL circuit. The speed
discriminator circuit outputs (This counts a single FG period.) an error signal once every two FG periods. The PLL
circuit outputs an error signal once every one FG Period. As compared to the earlier technique in which only a speed
discriminator circuit was used, the combination of a speed discriminator and a PLL circuit allows variations in motor
speed to be better suppressed when a motor that has large load variations is used. The FG servo frequency (fFG) is
determined by the frequency relationship shown below and by the clock signal (fCLK) input to the CCLK pin.
f_FG = (VCO divisor ÷ speed discriminator count) × f_CLK
N1
High or open
High or open
Low
Low
N2
High or open
Low
High or open
Low
Count
1024
1024
256
512
Divisor
1024
512
256
512
Therefore it is possible to implement half-speed control without switching the clock frequency by using combinations
of the N1 = high, N2 = low state and other setting states.
2. VCO Circuit
The LB11923V includes a built-in VCO circuit to generate the speed discriminator circuit reference signal. The
reference signal frequency is given by the following formula.
f_VCO = f_CLK × divisor f_VCO: Reference signal frequency
f_CLK: Externally input clock frequency
The range over which the reference signal frequency can be varied is determined by the resistor and capacitor
components connected to the R and C pins (pins 20 and 21) and by the VCO loop filter constant (the values of the
external components connected to pin 19).
Supply voltage
When V_CC is 5 V
When V_CC is 6.3 V
R (kΩ)
7.5
11
C (pF)
200
200
To acquire the widest possible range, it is better to use 6.3 V than 5 V as the supply voltage. It is also possible to
handle an even wider range than is possible with fixed counts by making the speed discriminator count and the VCO
divisor switchable.
The components connected to the R, C, and FIL pins must be connected with lines to their ground pins (pins 29 and
30) that are as short as possible.
3. Output Drive Circuit
To reduce power loss in the output, this IC adopts the direct PWM drive technique. The output transistors (which are
external to the IC) are always saturated when on, and the motor drive output is adjusted by changing the duty with
which the output is on. The PWM switching is performed on the high side for each phase (UH, VH, and WH). The
PWM switching side in the output can be selected to be either the high or low side depending on how the external
transistors are connected.
4. Current Limiter Circuit
The current limiter circuit limits the (peak) current at the value I = V_RF/R_f (V_RF = 0.26 V (typical), R_f: current
detection resistor). The current limitation operation consists of reducing the output duty to suppress the current.
High accuracy detection can be achieved by connecting the RF and RFGND pin lines near the ends of the current
detection resistor (Rf).
5. Speed Lock Range
The speed lock range is ±6.25% of the fixed speed. When the motor speed is in the lock range, the LD pin (an open
collector output) goes low. If the motor speed goes out of the lock range, the motor on duty is adjusted according to
the speed error to control the motor speed to be within the lock range.
No. 7498-16/20