PCA9535E_15 Datasheet, PDF (15/20 Pages) ON Semiconductor – 16-bit Low-Power I/O Expander

PCA9535E, PCA9535EC
System Configuration
A device generating a message is a ‘transmitter’; a device
receiving is the ‘receiver’. The device that controls the
message is the ‘master’ and the devices which are controlled
by the master are the ‘slaves’ (see Figure 16).
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
I²C−BUS
MULTIPLEXER
SLAVE
Figure 16. System Configuration
Acknowledge
The number of data bytes transferred between the START
and the STOP conditions from transmitter to receiver is not
limited. Each 8−bit byte is followed by one acknowledge bit.
The acknowledge bit is a HIGH level put on the bus by the
transmitter, whereas the master generates an extra clock
pulse for the acknowledge bit.
A slave receiver which is addressed must generate an
acknowledge after the reception of each byte. Also a master
must generate an acknowledge after the reception of each
byte that has been clocked out of the slave transmitter. The
device that acknowledges has to pull down the SDA line
during the acknowledge clock pulse, such that the SDA line
is stable LOW during the HIGH period of the acknowledge
clock pulse; set−up time and hold time must be taken into
account.
A master receiver signals an end of data to the transmitter
by not generating an acknowledge on the last byte that has
been clocked out of the slave. In this event, the transmitter
must leave the data line HIGH to enable the master to
generate a STOP condition.
data output
by transmitter
not acknowledge
data output
by receiver
acknowledge
SCL from master
1
2
8
9
S
START
condition
clock pulse for
acknowledgement
Figure 17. Acknowledgement of the I²C Bus
Timing and Test Setup
SDA
t_BUF
t_r
t_f
t_LOW
SCL
t_HD;STA
t_HD;STA
P
S
t_HD;DAT
t_HIGH
t_SU;DAT
t_SU;STA
Sr
Figure 18. Definition of Timing on the I²C Bus
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t_SP
t_SU;STO
P