PCA9535E_15 Datasheet, PDF (1/20 Pages) ON Semiconductor – 16-bit Low-Power I/O Expander

PCA9535E, PCA9535EC
16-bit Low-Power I/O
Expander for I²C Bus with
Interrupt
The PCA9535E and PCA9535EC devices provide 16 bits of
General Purpose parallel Input / Output (GPIO) expansion through the
I²C−bus / SMBus.
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The PCA9535E and PCA9535EC consist of two 8−bit
MARKING
Configuration (Input or Output selection); Input, Output and Polarity
DIAGRAMS
Inversion (active−HIGH or active−LOW operation) registers. At
power on, all I/Os default to inputs. Each I/O may be configured as
either input or output by writing to its corresponding I/O configuration
bit. The data for each Input or Output is kept in its corresponding Input
or Output register. The Polarity Inversion register may be used to
invert the polarity if the read register. All registers can be read by the
SOIC−24
DW SUFFIX
CASE 751E
PCA9535E(C)
AWLYYWWG
system master.
The PCA9535E, identical to the PCA9655E but with the internal
I/O pull−up resistors removed, has greatly reduced power
consumption when the I/Os are held LOW.
The PCA9535EC is identical to the PCA9535E but with
high−impedance open−drain outputs at all the I/O pins.
The PCA9535E and PCA9535EC provide an open−drain interrupt
output which is activated when any input state differs from its
TSSOP−24
DT SUFFIX
CASE 948H
PCA95
35E(C)G
ALYW
corresponding input port register state. The interrupt output is used to
indicate to the system master that an input state has changed. The
power−on reset sets the registers to their default values and initializes
the device state machine.
Three hardware pins (AD0, AD1, AD2) are used to configure the
I²C−bus slave address of the device. The I²C−bus slave addresses of
1
WQFN24
MT SUFFIX
CASE 485BG
PCA
9535E(C)
ALYWG
G
the PCA9535E and PCA9535EC are the same as the PCA9655E. This
allows up to 64 of these devices in any combination to share the same
I²C−bus/SMBus.
XXXX
A
WL, L
YY, Y
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
Features
• V_DD Operating Range: 1.65 V to 5.5 V
• SDA Sink Capability: 30 mA
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
• 5.5 V Tolerant I/Os
• Polarity Inversion Register
• Active LOW Interrupt Output
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
• Low Standby Current
• Noise Filter on SCL/SDA Inputs
• ESD Performance: 3000 V Human Body Model, 400 V
• No Glitch on Power−up
• Internal Power−on Reset
Machine Model
• NLV Prefix for Automotive and Other Applications
• 64 Programmable Slave Addresses using Three
Address Pins
• 16 I/O Pins which Default to 16 Inputs
• I²C SCL Clock Frequencies Supported:
Requiring Unique Site and Control Change
Requirements; AEC−Q100 Qualified and PPAP
Capable
• These are Pb−Free Devices
Standard Mode: 100 kHz
Fast Mode: 400 kHz
Fast Mode +: 1 MHz
© Semiconductor Components Industries, LLC, 2015
1
October, 2015 − Rev. 6
Publication Order Number:
PCA9535E/D