NCP1083 Datasheet, PDF (15/17 Pages) ON Semiconductor – Integrated High Power PoE-PD Interface & DC-DC Converter Controller with 9V Auxiliary Supply Support

NCP1083
When VPORT reaches the UVLO_on level, the Cpd
capacitor is charged with the INRUSH current (in order to
limit the internal power dissipation of the pass−switch).
Once the Cpd capacitor is fully charged, the current limit
switches from the inrush current to the current level (ilim1)
as shown in Figure 15. This transition occurs when both
following conditions are satisfied:
1. The VDS of the pass−switch is below the
Vds_pgood low level (1 V typical).
2. The pass−switch is no longer in current limit
mode, meaning the gate of the pass−switch is
“high” (above 2 V typical).
The operational current limit will stay selected as long as
Vds_pgood is true (meaning that RTN−VPORTN_1,2 is
below the high level of Vds_pgood). This mechanism allows
a current level transition without any current spike in the
pass−switch because the operational current limit (ilim1) is
enabled once the pass−switch is not limiting the current
anymore, meaning that the Cpd capacitor is fully charged.
VDDL
Thermal Shutdown
The NCP1083 includes thermal protection which shuts
down the device in case of high power dissipation. Once the
thermal shutdown (TSD) threshold is exceeded, following
blocks are turned off:
• DC−DC controller
• Pass−switch
• VDDH and VDDL regulators
• CLASS regulator
When the TSD error disappears and if the input line
voltage is still above the UVLO level, the NCP1083
automatically restarts with the current limit set in the inrush
state, the DC−DC controller is disabled and the Css
(soft−start capacitor) discharged. The DC−DC controller
becomes operational as soon as capacitor Cpd is fully
charged.
DC−DC Converter Controller
The NCP1083 implements a current mode DC−DC
converter controller which is illustrated in Figure 16.
OSC
VPORTP
FB
COMP
CS
1.2 V
5 kW
Oscillator
&
Sawtooth
Generator
Reset Set
CLK CLK
Current Slope
Compensation
11 kW
Blanking
time
VDDL
5 mA
10 mA
0
1.45 V
2
PWM comp
Current limit
comp
360 mV
S
Q
R
3.3 V LDO
9 V LDO
Gate
Driver
VDDL
VDDH
GATE
ARTN
SS
Soft−start
Figure 16. DC−DC Controller Block Diagram
Internal VDDH and VDDL Regulators and Gate Driver
An internal linear regulator steps down the VPORTP
voltage to a 9 V output on the VDDH pin. VDDH supplies
the internal gate driver circuit which drives the GATE pin
and the gate of the external power MOSFET. The NCP1083
gate driver supports an external MOSFET with high Vth and
high input gate capacitance. A second LDO regulator steps
down the VDDH voltage to a 3.3 V output on VDDL. VDDL
powers the analog circuitry of the DC-DC controller and
nCLASS_AT blocks. Moreover it can provide current to
light a LED connected on the nCLASS_AT pin.
In order to prevent uncontrolled operations, both regulators
include power−on−reset (POR) detectors which prevent the
DC−DC controller from operating when either VDDH or
VDDL is too low. In addition, an over−voltage lockout
(OVLO) on the VDDH supply disables the gate driver in case
of an open−loop converter with a configuration using the bias
winding of the transformer (see Figure 4).
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