MT9V024 Datasheet, PDF (15/62 Pages) ON Semiconductor – Wide-VGA CMOS Digital Image Sensor

MT9V024: 1/3-Inch Wide-VGA Digital Image Sensor
Output Data Format
Table 2:
Frame Time (continued)
Parameter
A+Q
V
Nrows x (A + Q)
F
Name
Row time
Vertical blanking
Frame valid time
Total frame time
Equation
Context A: R0x04 + R0x05
Context B: R0xCC + R0xCD
Context A: (R0x06) x (A + Q) + 4
Context B: (R0xCE) x (A + Q) + 4
Context A: (R0x03) × (A + Q)
Context B: (R0xCB) x (A + Q)
V + (Nrows x (A + Q))
Default Timing at 26.66 MHz
846 pixel clocks
= 846 master
= 31.72s
38,074 pixel clocks
= 38,074 master
= 1.43ms
406,080 pixel clocks
= 406,080 master
= 15.23ms
444,154 pixel clocks
= 444,154 master
= 16.66ms
Sensor timing is shown above in terms of pixel clock and master clock cycles (refer to
Figure 8 on page 9). The recommended master clock frequency is 26.66 MHz. The
vertical blanking and the total frame time equations assume that the integration time
(coarse shutter width plus fine shutter width) is less than the number of active rows plus
the blanking rows minus the overhead rows:
Window Height + Vertical Blanking – 2
(EQ 1)
If this is not the case, the number of integration rows must be used instead to determine
the frame time, as shown in Table 3. In this example, it is assumed that the coarse shutter
width control is programmed with 523 rows and the fine shutter width total is zero.
For Simultaneous mode, if the exposure time registers (coarse shutter width total plus
Fine Shutter Width Total) exceed the total readout time, then the vertical blanking time
is internally extended automatically to adjust for the additional integration time
required. This extended value is not written back to the vertical blanking registers. The
vertical blank register can be used to adjust frame-to-frame readout time. This register
does not affect the exposure time but it may extend the readout time.
Table 3:
Frame Time—Long Integration Time
Parameter Name
Vertical blanking (long
V’
integration time)
Total frame time (long
F’
integration time)
Equation
(Number of Master Clock Cycles)
Context A: (R0x0B + 2 - R0x03) × (A + Q) + R0xD5 + 4
Context B: (R0xD2 + 2 - R0xCB) x (A + Q) + R0xD8 + 4
Context A: (R0x0B + 2) × (A + Q) + R0xD5 + 4
Context B: (R0xD2 + 2) x (A + Q) + R0xD8 + 4
Default Timing
at 26.66 MHz
38,074 pixel clocks
= 38,074 master
= 1.43ms
444,154 pixel clocks
= 444,154 master
= 16.66ms
Note:
The MT9V024 uses column parallel analog-digital converters; thus short row timing is not possi-
ble. The minimum total row time is 704 columns (horizontal width + horizontal blanking). The
minimum horizontal blanking is 61 for normal mode, 71 for column bin 2 mode, and 91 for col-
umn bin 4 mode. When the window width is set below 643, horizontal blanking must be
increased. In binning mode, the minimum row time is R0x04+R0x05 = 704.
MT9V024_DSRev. G Pub. 4/15 EN
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