MC10EP446 Datasheet, PDF (15/20 Pages) ON Semiconductor – 3.3V/5V 8­Bit CMOS/ECL/TTL Data Input Parallel/Serial Converter

MC10EP446, MC100EP446
The differential synchronous CKEN inputs (Pins 6 and 7), disable the internal clock circuitry. The synchronous CKEN will
suspend all of the device activities and prevent runt pulses from being generated. The rising edge of CKEN followed by the
falling edge of CLK will suspend all activities. The falling edge of CKEN followed by the falling edge of CLK will resume
all activities (Figure 12).
Internal Clock
Disabled
Internal Clock
Enabled
CLK
CKEN
SOUT
PCLK
CKSEL
D0−1
D1−1
D2−1
D3−1 D4−1 D5−1
Figure 12. Timing Diagram with CKEN with CKSEL HIGH
The differential PCLK output (Pins 14 and 15) is a word
framer and can help the user synchronize the serial data
output, S_OUT (Pins 11 and 12), in their applications.
Furthermore, PCLK can be used as a trigger for input
parallel data (Figure 13).
An internally generated voltage supply, the V_BB pin, is
available to this device only. For single–ended input
conditions, the unused differential input is connected to V_BB
as a switching reference voltage. V_BB may also rebias AC
coupled inputs. When used, decouple V_BB and V_CC via a
0.01 mF capacitor and limit current sourcing or sinking to
0.5 mA. When not used, V_BB should be left open. Also, both
outputs of the differential pair must be terminated (50 W to
V_TT) even if only one output is used.
CLK RESET
Pattern Generator
Data Format Logic
(FPGA, ASIC)
TRIGGER
CLK
SYNC
EP446
S_OUT SERIAL DATA
PCLK
Figure 13. PCLK as Trigger Application
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