NCP1607BOOSTGEVB Datasheet, PDF (14/23 Pages) ON Semiconductor – Cost Effective Power Factor Controller

NCP1607
To prevent negative voltages on the ZCD pin, the pin is
internally clamped to V_CL(NEG) (600 mV typical) when the
ZCD winding is negative. Similarly, the ZCD pin is
clamped to V_CL(POS) (5.7 V typical), when the voltage rises
too high. Because of these clamps, a resistor (R_ZCD in
Figure 29) is necessary to limit the current from the ZCD
winding to the ZCD pin.
At startup, there is no energy in the ZCD winding and
therefore no voltage signal to activate the ZCD
comparators. This means that the driver could never turn
on. Therefore, to enable the PFC stage to startup under
these conditions, an internal watchdog timer is integrated
into the controller. This timer turns the drive on if the driver
has been off for more than 180 ms (typical). This feature is
deactivated during a fault mode (OVP, UVP, or Shutdown),
and reactivated when the fault is removed.
STARTUP
Generally, a resistor connected between the ac input and
V_CC (pin 8) charges the V_CC capacitor to the V_CC(on) level
(12 V typical). Because of the very low consumption of the
NCP1607 during this stage (< 40 mA), most of the current
goes directly to charging up the V_CC capacitor. This
provides faster startup times and reduced standby power
dissipation. When the V_CC voltage exceeds the V_CC(on)
level, the internal references and logic of the NCP1607 turn
on. The controller has an undervoltage lockout (UVLO)
feature which keeps the part active until V_CC drops below
V_CC(off) (9.5 V typical). This hysteresis allows ample time
for the auxiliary winding to take over and supply the
necessary power to V_CC (Figure 30).
V_CC(on)
V_CC(off)
V_CC
Figure 30. Typical V_CC Startup Waveform
When the PFC pre−converter is loaded by a switch mode
power supply (SMPS), then it is often preferable to have the
SMPS controller startup first. The SMPS can then supply
the NCP1607 V_CC directly. Advanced controllers, such as
the NCP1230 or NCP1381, can control when to turn on the
PFC stage (see Figure 31) leading to optimal system
performance. This setup also eliminates the startup
resistors and therefore improves the no load power
dissipation of the system.
D_BOOST
+
C_BULK
PFC_V_CC
1
8
1
8
+
2
7
2
7
3
6
V_CC
3
6
4
5
4
5+
NCP1230
+
+
Figure 31. NCP1607 Supplied by a Downstream SMPS Controller (NCP1230)
QUICK START and SOFT START
At startup, the error amplifier is enabled and Control is
pulled up to V_EAL (2.1 V typical). This is the lowest level
of control voltage which produces output drives. This
feature, called “quick start,” eliminates the delay at startup
associated with charging the compensation network to its
minimum level. This also produces a natural “soft−start”
mode where the controller’s power ramps up from zero to
the required power (see Figure 32).
www.onsemi.com
14