LE25W81QE Datasheet, PDF (14/21 Pages) ON Semiconductor – Serial Flash Memory

LE25W81QE
11. Hold Function
Using the HOLD pin, the hold function suspends serial communication (it places it in the hold status). "Figure 17
HOLD" shows the timing waveforms. The device is placed in the hold status at the falling HOLD edge while the logic
level of SCK is low, and it exits from the hold status at the rising HOLD edge. When the logic level of SCK is high,
HOLD must not rise or fall. The hold function takes effect when the logic level of CS is low, the hold status is exited
and serial communication is reset at the rising CS edge. In the hold status, the SO output is in the high-impedance state,
and SI and SCK are "don't care".
Figure 17 HOLD
CS
SCK
HOLD
SO
Active
tHS
HOLD
Active
tHS
tHH
tHH
tHHZ
High Impedance
tHLZ
12. Power-on
In order to protect against unintentional writing, CS must be kept at VDD At power-on. After power-on, the supply
voltage has stabilized at 2.70V or higher, wait for 100s (tPU_READ) before inputting the command to start a read
operation. Similarly, wait for 10ms (tPU_WRITE) after the voltage has stabilized before inputting the command to start
a write operation.
Figure 18 Power-on Timing
VDD
VDD(Max)
Program, Erase and Write Command not Allowed
Chip selection not Allowed Read Access Allowed
Full Access Allowed
VDD(Min)
0V
tPU_READ
tPU_WRITE
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