NCP1573 Datasheet, PDF (13/17 Pages) ON Semiconductor – Low Voltage Synchronous Buck Controller

NCP1573
IIN(AVE) + (10 A)(3.3 Vń5 V) + 6.6 A
Input capacitor RMS ripple current is then
Ǹ ^{IIN(RMS) +}
6.62
)
3.3 V
5V
[(10 A * 6.6 A)2 * 6.6 A2]
+ 4.74 A
If we consider a Rubycon MBZ series capacitor, the ripple
current rating for a 6.3 V, 1800 nF capacitor is 2000 mA at
100 kHz and 105°C. We determine the number of input
capacitors by dividing the ripple current by the
per−capacitor current rating:
Number of capacitors + 4.74 Ań2.0 A + 2.3
A total of at least 3 capacitors in parallel must be used to
meet the input capacitor ripple current requirements.
Output Switch FETs
Output switch FETs must be chosen carefully, since their
properties vary widely from manufacturer to manufacturer.
The NCP1573 system is designed assuming that n−channel
FETs will be used. The FET characteristics of most concern
are the gate charge/gate−source threshold voltage, gate
capacitance, on−resistance, current rating and the thermal
capability of the package.
The onboard FET driver has a limited drive capability. If
the switch FET has a high gate charge, the amount of time
the FET stays in its ohmic region during the turn−on and
turn−off transitions is larger than that of a low gate charge
FET, with the result that the high gate charge FET will
consume more power. Similarly, a low on−resistance FET
will dissipate less power than will a higher on−resistance
FET at a given current. Thus, low gate charge and low
R_DS(ON) will result in higher efficiency and will reduce
generated heat.
It can be advantageous to use multiple switch FETs to
reduce power consumption. By placing a number of FETs in
parallel, the effective R_DS(ON) is reduced, thus reducing the
ohmic power loss. However, placing FETs in parallel
increases the gate capacitance so that switching losses
increase. As long as adding another parallel FET reduces the
ohmic power loss more than the switching losses increase,
there is some advantage to doing so. However, at some point
the law of diminishing returns will take hold, and a marginal
increase in efficiency may not be worth the board area
required to add the extra FET. Additionally, as more FETs
are used, the limited drive capability of the FET driver will
have to charge a larger gate capacitance, resulting in
increased gate voltage rise and fall times. This will affect the
amount of time the FET operates in its ohmic region and will
increase power dissipation.
The following equations can be used to calculate power
dissipation in the switch FETs.
For ohmic power losses due to R_DS(ON):
PON(TOP)
+
(RDS(ON)(TOP))(IRMS(TOP))2
(number of topside FETs)
PON(BOTTOM)
+
ǒ_{RDS(ON)(BOTTOM)}Ǔǒ_IRMS(BOTTOM)Ǔ2
ǒ_{number of bottom−side FETs}Ǔ
where:
n = number of phases.
Note that R_DS(ON) increases with temperature. It is good
practice to use the value of R_DS(ON) at the FET’s maximum
junction temperature in the calculations shown above.
Ǹ IRMS(TOP) +
I^2PK
*
(IPK)(IRIPPLE)
)
D
3
I^2RIPPLE
IRMS(BOTTOM)
+
I^2PK
*
(IPKIRIPPLE)
)
(1
*
3
D)
I
2
RIPPLE
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