NCP1631 Datasheet, PDF (12/23 Pages) ON Semiconductor – Interleaved, 2-Phase Power Factor Controller

NCP1631
Provided the low bandwidth of the regulation loop, sharp
variations of the load, may result in excessive over and
under−shoots. Over−shoots are limited by the Over−
Voltage Protection (see OVP section). To contain the
under−shoots, an internal comparator monitors the
feed−back signal (V_pin2) and when V_pin2 is lower than
95.5% of its nominal value, it connects a 230 mA current
source to speed−up the charge of the compensation
capacitor (C_pin5). Finally, it is like if the comparator
multiplied the error amplifier gain by 10.
One must note that this circuitry for under−shoots
limitation, is not enabled during the start−up sequence of
the PFC stage but only once the converter has stabilized
(that is when the “pfcOK” signal of the block diagram, is
high). This is because, at the beginning of operation, the
pin5 capacitor must charge slowly and gradually for a soft
start−up.
Zero Current Detection
While the on time is constant, the core reset time varies
with the instantaneous input voltage. The NCP1631
determines the demagnetization completion by sensing the
inductor voltage, more specifically, by detecting when the
inductor voltage drops to zero.
Practically, an auxiliary winding in flyback
configuration is taken off of the boost inductor and gives a
scaled down version of the inductor voltage that is usable
by the controller (Figure 12). In that way, the ZCD voltage
(“V_AUX”) falls and starts to ring around zero volts when the
inductor current drops to zero. The NCP1631 detects this
falling edge and allows the next driver on time.
Figure 1 shows how it is implemented.
For each phase, a comparator detects when the voltage
of the ZCD winding exceeds 0.5 V. When this is the case,
the coil is in demagnetization phase and the latch L_ZCD is
set. This latch is reset when the next driver pulse occurs.
Rzcd2
1 ZCD2
Negative
and
positive
clamp
16 ZCD1
Rzcd1
D1
Vin
Negative
and
positive
clamp
+
−
0.5 V
OFF
V_DMG1
AND1
Vzcd1
PWM
SET1 ^latch
S ^Qzcd1
PH1 Vcc
Q
L_{ZCD QZCD}
R
CLK1
S
Q
R
(from phase
management ^In−rush
output
buffe r 1
block)
200−ms
reset signal
de lay
S
DT
Q
R
(from PH1 PWM
comparator)
(from Fault
L1
DRV1
14 M1
D2 Vout
Vin L2
management
block)
V_DMG2
+
−
0.5 V
Vzcd2
PWM
output
SET2 _{latch PH2 buffe r 2}
S ^Qzcd2
Q
CLK2
R
(from phase
S
Vcc
Q
R
management ^In−rush
reset signal
DRV2
Cbulk
11 M2
Cbulk
block) (from PH2 PWM comparator)
Figure 11. Zero Current Detection
To prevent negative voltages on the ZCD pins (ZCD1 for
phase 1 and ZCD2 for phase 2), these pins are internally
clamped to about 0 V when the voltage applied by the
corresponding ZCD winding is negative. Similarly, the
ZCD pins are clamped to V_ZCD(high) (10 V typical), when
the ZCD voltage rises too high. Because of these clamps,
a resistor (R_ZCD of Figure 11) is necessary to limit the
current from the ZCD winding to the ZCD pin. The clamps
are designed to respectively source and sink 5 mA
minimum. It is recommended not to exceed this 5 mA level
within the ZCD clamps for a proper operation.
At startup or after an inactive period (because of a
protection that has tripped for instance), there is no energy
in the ZCD winding and therefore no voltage signal to
activate the ZCD comparator. This means that the driver
will never turn on. To avoid this, an internal watchdog
timer is integrated into the controller. If the driver remains
low for more than 200 ms (typical), the timer sets the L_ZCD
latch as the ZCD winding signal would do. Obviously, this
200−ms delay acts as a minimum off−time if there is no
demagnetization winding while it has no action if there is
a ZCD voltage provided by the auxiliary winding.
http://onsemi.com
12