NCP1612A Datasheet, PDF (10/33 Pages) ON Semiconductor – Enhanced, High‐Efficiency Power Factor Controller

NCP1612A, NCP1612B, NCP1612A1, NCP1612A2, NCP1612A3, NCP1612B2
BUVcomp
BUVcomp2
BUV
BUVcomp2
BUVcomp1
V _BUV
FB
NCP1612A
NCP1612A1
pfcOK
12%*Vref
+
hyst<1%Vref
−
NCP1612A3
and NCP1612B
UVP
Internal
Thermal
Shutdown
Vref
VDD
Vcc
Regul
UVP2
TSD
STDWN
Iref
UVP
+
105%*Vref /
−
103% *Vref
softOVP
BO_fault
BO_NOK
OFF
staticOVP
Dynamic Response
Enhancer
pfcOK
0.955*Vref
hyst<0.5%Vref
200 mA
Fault
management
Vcontrol
Error Amplifier
+/−20mA
Vref
OVLflag1
0.5−V bottom clamp
VDD
OFF
50mA
4V
0.5V
staticOVP
(0.5−V bottom
clamp
is activated)
V _REGUL
0.5V
OFF
UVLO
Vcc_OK
Vcc(on) / Vcc(off)
fastOVP
107% Vref
hyst<1% Vref
FOVP
UVP2
BUVcomp1
12*Vref
V _BUV
BONOK
staticOVP
S
Q
L _BO
R
BUV
staticOVP
S
Q
L _BUV
R
BUV_fault
FFcontrol
I _BO
I _REGUL Overstress
Current Information
Generator and
dead−time control
LLine DRV ZCD
BUVcomp
OVLflag1
OFF
BUV_fault
pfcOK
S
Q
LpfcOK
R
OCP
NCP1612A2 and NCP1612B2
STOP
fastOVP
GND
staticOVP
DT
SKIP
softOVP
Vton
processing
circuitry
LLine
Internal
timing
ramp
DT
CLK
SKIP
DRV
CCFF mode
(including SKIP function)
are inhibited whenever
pfcOK_in is low
fastOVP
pfcOK_in
OFF
Overstress
CLK
Vpwm
S
Q
L
pwm1
R
Vcc
Output
Buffer
DRV
STOP
All the RS latches are
RESET dominant
DRV
DRV
200−ns
CS
OCP
Detection
blanking
+
time
Overstress
of excessive
currents
−
500mV
ZCD
NCP1612A
NCP1612A1
NCP1612A3
and NCP1612B
DRV
100−ns
blanking
+
time
−
750mV /
250mV
LLine
BO_NOK
2R
+
R
2.5 V
−
NCP1612A2 and
NCP1612B2
Vcc(reset)
BONOK
Vcc_OK
S
Q
Lstdwn
R
STDWN
Brown−out
and Line Range
Detection
BO
I _BO
Figure 3. Block Diagram
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