NTD4969N_14 Datasheet, PDF (1/7 Pages) ON Semiconductor – Power MOSFET

NTD4969N
Power MOSFET
30 V, 41 A, Single N−Channel, DPAK/IPAK
Features
• Low R_DS(on) to Minimize Conduction Losses
• Low Capacitance to Minimize Driver Losses
• Optimized Gate Charge to Minimize Switching Losses
• Three Package Variations for Design Flexibility
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Applications
• CPU Power Delivery
• DC−DC Converters
MAXIMUM RATINGS (T_J = 25°C unless otherwise stated)
Parameter
Symbol Value Unit
Drain−to−Source Voltage
Gate−to−Source Voltage
Continuous Drain
Current R_qJA
(Note 1)
V_DSS
30
V
V_GS
±20
V
T_A = 25°C
I_D
12.7
A
T_A = 100°C
9.0
Power Dissipation
R_qJA (Note 1)
T_A = 25°C
P_D
Continuous Drain
T_A = 25°C
I_D
Current R_qJA
(Note 2)
Steady TA = 100°C
State
Power Dissipation
T_A = 25°C
P_D
R_qJA (Note 2)
Continuous Drain
Current R_qJC
(Note 1)
T_C = 25°C
I_D
T_C = 100°C
2.56 W
9.4
A
6.6
1.38 W
41
A
29
Power Dissipation
R_qJC (Note 1)
T_C = 25°C
P_D
26.3 W
Pulsed Drain
Current
t_p=10ms T_A = 25°C
I_DM
150
A
Current Limited by Package
T_A = 25°C
Operating Junction and Storage
Temperature
Source Current (Body Diode)
Drain to Source dV/dt
Single Pulse Drain−to−Source Avalanche
Energy (T_J = 25°C, V_DD = 24 V, V_GS = 10 V,
I_L = 19 A_pk, L = 0.1 mH, R_G = 25 W)
Lead Temperature for Soldering Purposes
(1/8” from case for 10 s)
I_DmaxPkg
T_J,
T_STG
I_S
dV/dt
EAS
40
−55 to
+175
24
6.0
18
A
°C
A
V/ns
mJ
T_L
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu.
2. Surface−mounted on FR4 board using the minimum recommended pad size.
http://onsemi.com
V_(BR)DSS
30 V
R_DS(ON) MAX
9.0 mW @ 10 V
19 mW @ 4.5 V
D
I_D MAX
41 A
G
S
N−CHANNEL MOSFET
4
4
4
12
3
CASE 369AA
DPAK
(Bent Lead)
STYLE 2
1 ₂₃
1
2
3
CASE 369AC CASE 369D
3 IPAK
IPAK
(Straight Lead) (Straight Lead
DPAK)
4
Drain
MARKING DIAGRAMS
& PIN ASSIGNMENTS
4
Drain
4
Drain
2
1 ^Drain 3
Gate Source
1 23
Gate Drain Source
1
23
Gate Drain Source
A
= Assembly Location
Y
= Year
WW = Work Week
4969N = Device Code
G
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
1
May, 2014 − Rev. 2
Publication Order Number:
NTD4969N/D