NSB1010XV5T5 Datasheet, PDF (1/6 Pages) ON Semiconductor – Dual Common Base−Collector Bias Resistor Transistors

NSB1010XV5T5
Preferred Device
Dual Common
Base−Collector Bias
Resistor Transistors
NPN and PNP Silicon Surface Mount
Transistors with Monolithic Bias
Resistor Network
The BRT (Bias Resistor Transistor) contains a single transistor with
a monolithic bias network consisting of two resistors; a series base
resistor and a base−emitter resistor. These digital transistors are
designed to replace a single device and its external resistor bias
network. The BRT eliminates these individual components by
integrating them into a single device. In the NSB1010XV5T5, two
complementary BRT devices are housed in the SOT−553 package
which is ideal for low power surface mount applications where board
space is at a premium.
• Simplifies Circuit Design
• Reduces Board Space
• Reduces Component Count
• Available in 8 mm, 7 inch Tape and Reel
• This device is manufactured with a Pb−Free external lead finish only.
MAXIMUM RATINGS (T_A = 25°C unless otherwise noted, common for Q₁
and Q₂, − minus sign for Q₁ (PNP) omitted)
Rating
Symbol
Value
Unit
Collector-Base Voltage
V_CBO
50
Vdc
Collector-Emitter Voltage
V_CEO
50
Vdc
Collector Current
I_C
100
mAdc
THERMAL CHARACTERISTICS
Characteristic
(One Junction Heated)
Symbol
Max
Unit
Total Device Dissipation
T_A = 25°C
Derate above 25°C
Thermal Resistance
Junction-to-Ambient
P_D
R_qJA
357 (Note 1)
2.9 (Note 1)
350 (Note 1)
mW
mW/°C
°C/W
Characteristic
(Both Junctions Heated)
Symbol
Max
Unit
Total Device Dissipation
T_A = 25°C
Derate above 25°C
P_D
500 (Note 1) mW
4.0 (Note 1) mW/°C
Thermal Resistance
Junction-to-Ambient
R_qJA 250 (Note 1) °C/W
Junction and Storage Temperature
T_J, T_stg −55 to +150
°C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. FR−4 @ Minimum Pad.
http://onsemi.com
3
2
1
R1
R2
Q2
R2
Q1
R1
4
5
MARKING
5
DIAGRAM
1
SOT−553
CASE 463B
5
US D
1
US = Specific Device Code
D = Date Code
ORDERING INFORMATION
Device
Package
Shipping^†
NSB1010XV5T5 SOT−553
2 mm pitch
(Pb−Free) 8000/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Preferred devices are recommended choices for future use
and best overall value.
 Semiconductor Components Industries, LLC, 2005
1
January, 2005 − Rev. 0
Publication Order Number:
NSB1010XV5/D