NOII5SM1300A Datasheet, PDF (1/33 Pages) ON Semiconductor – IBIS5 1.3 Megapixel CMOS Image Sensor

NOII5SM1300A
IBIS5 1.3 Megapixel CMOS
Image Sensor
Features
• 1280 x 1024 Active Pixels
• 6.7 mm x 6.7 mm Square Pixels
• 2/3” Optical Format
• Global and Rolling Shutter
• Master Clock: 40 MHz
• 27 fps (1280 x 1024) and 106 fps (640 x 480)
• On-chip 10-bit ADCs
• Serial Peripheral Interface (SPI)
• Windowing (ROI)
• Sub-sampling: 1:2 Mode
• Supply Voltage
♦ Analog: 3.0 V to 4.5 V
♦ Digital: 3.3 V
♦ I/O: 3.3 V
• Power Consumption: 200 mW
• −30°C to +65°C Operating Temperature Range
• 84-pin LCC Package
• These Devices are Pb−Free and are RoHS Compliant
Applications
• Machine Vision
• Inspection
• Robotics
• Traffic Monitoring
http://onsemi.com
Figure 1. IBIS5−1300 Photo
Description
The IBIS5-1300 is a solid state CMOS image sensor that integrates the functionality of complete analog image acquisition,
digitizer, and digital signal processing system on a single chip. This 1.3-mega pixel (1280 x 1024) CMOS active pixel sensor
dedicated to industrial vision applications features both rolling and snapshot (or global) shutter. Full frame readout time is
36 ms (max. 27.5 fps), and readout speed are boosted by windowed region of interest (ROI) readout. Another feature includes
the double and multiples slope functionality to capture high dynamic range scenes. The sensor is available in a monochrome
version or Bayer (RGB) patterned color filter array.
User programmable row and column start/stop positions allow windowing down to a 2x1 pixel window for digital zoom.
Sub sampling or viewfinder mode reduces resolution while maintaining the constant field of view and an increased frame
rate. An on-chip analog signal pipeline processes the analog video output of the pixel array. Double sampling (DS) eliminates
the fixed pattern noise. The programmable gain and offset amplifier maps the signal swing to the ADC input range. A 10-bit
ADC converts the analog data to a 10-bit digital word stream. The sensor uses a 3-wire serial peripheral interface (SPI), or a
16-bit parallel interface. It operates with a 3.3 V power supply and requires only one master clock for operation up to 40 MHz.
It is housed in an 84-pin ceramic LCC package.
ORDERING INFORMATION
Marketing Part Number
NOII5SM1300A-QDC
NOII5SM1300A-QWC
NOII5SC1300A-QDC
NOII5FM1300A-QDC
Description
Mono with glass
Mono without glass
Color with glass
Mono on thicker epitaxial layer, with glass
NOTE: See Ordering Code Information on page 33 for more information.
Package
84−pin LCC
Device Status
End−of−Life (EOL)
Last Time Buy
PCN Close date:
October 29, 2011
© Semiconductor Components Industries, LLC, 2013
1
May, 2013 − Rev. 12
Publication Order Number:
NOII5SM1300A/D