NB7L86M Datasheet, PDF (1/12 Pages) ON Semiconductor – 2.5V/3.3V 12 Gb/s Differential Clock/Data SmartGate with CML Output and Internal Termination

NB7L86M
2.5V/3.3V 12 Gb/s Differential
Clock/Data SmartGate with
CML Output and Internal
Termination
The NB7L86M is a multi−function differential Logic Gate, which
can be configured as an AND/NAND, OR/NOR, XOR/XNOR, or 2:1
MUX. This device is part of the GigaComm family of high
performance Silicon Germanium products. The NB7L86M is an
ultra−low jitter multi−logic gate with a maximum data rate of 12 Gb/s
and input clock frequency of 8 GHz suitable for Data Communication
Systems, Telecom Systems, Fiber Channel, and GigE applications.
Differential inputs incorporate internal 50 W termination resistors
and accept LVNECL (Negative ECL), LVPECL (Positive ECL),
LVCMOS, LVTTL, CML, or LVDS. The differential 16 mA CML
output provides matching internal 50 W termination, and 400 mV
output swing when externally terminated 50 W to VCC.
The device is housed in a low profile 3x3 mm 16−pin QFN package.
Application notes, models, and support documentation are available
on www.onsemi.com.
Features
• Maximum Input Clock Frequency up to 8 GHz
• Maximum Input Data Rate up to 12 Gb/s Typical
• < 0.5 ps of RMS Clock Jitter
• < 10 ps of Data Dependent Jitter
• 30 ps Typical Rise and Fall Times
• 90 ps Typical Propagation Delay
• 2 ps Typical Within Device Skew
• Operating Range: V_CC = 2.375 V to 3.465 V with V_EE = 0 V
• CML Output Level (400 mV Peak−to−Peak Output) Differential Output
• 50 W Internal Input and Output Termination Resistors
• Functionally Compatible with Existing 2.5 V/3.3 V LVEL, LVEP, EP
and SG Devices
• Pb−Free Packages are Available
VTD0
D0
50 W
D0
VTD0
50 W
VTD1
D1
50 W
http://onsemi.com
QFN−16
MN SUFFIX
CASE 485G
MARKING
DIAGRAM*
16
1
NB7L
86M
ALYWG
G
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
Q
Q
D1
VTD1
50 W
50 W 50 W
VTSEL
SEL
SEL
Figure 1. Simplified Logic Diagram
© Semiconductor Components Industries, LLC, 2006
1
January, 2006 − Rev. 3
Publication Order Number:
NB7L86M/D