MTB2N60E Datasheet, PDF (1/10 Pages) Motorola, Inc – TMOS POWER FET 2.0 AMPERES 600 VOLTS

MTB2N60E
Designer’s™ Data Sheet
TMOS E−FET.™
High Energy Power FET
D²PAK for Surface Mount
N−Channel Enhancement−Mode Silicon
Gate
http://onsemi.com
This high voltage MOSFET uses an advanced termination scheme
to provide enhanced voltage−blocking capability without degrading
performance over time. In addition, this advanced TMOS E−FET is
designed to withstand high energy in the avalanche and commutation
modes. The new energy efficient design also offers a drain−to−source
diode with a fast recovery time. Designed for high voltage, high speed
switching applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are critical
and offer additional safety margin against unexpected voltage
transients.
• Robust High Voltage Termination
• Avalanche Energy Specified
• Source−to−Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• I_DSS and V_DS(on) Specified at Elevated Temperature
TMOS POWER FET
2.0 AMPERES, 600 VOLTS
R_DS(on) = 3.8 W
CASE 418B−02, Style 2
D²PAK
D
®
G
S
MAXIMUM RATINGS (T_C = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain−to−Source Voltage
Drain−to−Gate Voltage (R_GS = 1.0 MΩ)
Gate−to−Source Voltage — Continuous
— Non−Repetitive (t_p ≤ 10 ms)
V_DSS
600
Vdc
V_DGR
600
Vdc
V_GS
± 20
Vdc
V_GSM
± 40
Vpk
Drain Current — Continuous
— Continuous @ 100°C
— Single Pulse (t_p ≤ 10 μs)
I_D
2.0
Adc
I_D
1.3
I_DM
7.0
Apk
Total Power Dissipation @ 25°C
Derate above 25°C
Total Power Dissipation @ T_A = 25°C ⁽¹⁾
P_D
50
Watts
0.4
W/°C
2.5
Watts
Operating and Storage Temperature Range
Single Pulse Drain−to−Source Avalanche Energy — Starting T_J = 25°C
(V_DD = 50 Vdc, V_GS = 10 Vdc, Peak I_L = 2.0 Apk, L = 95 mH, R_G = 25 Ω)
T_J, T_stg − 55 to 150
°C
E_AS
190
mJ
Thermal Resistance — Junction to Case
— Junction to Ambient
— Junction to Ambient ⁽¹⁾
R_θJC
R_θJA
R_θJA
2.5
°C/W
62.5
50
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
T_L
260
°C
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E−FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
© Semiconductor Components Industries, LLC, 2006
1
August, 2006 − Rev. 1
Publication Order Number:
MTB2N60E/D