MMUN2111LT1_05 Datasheet, PDF (1/8 Pages) ON Semiconductor – Bias Resistor Transistors

MMUN2111LT1 Series
Preferred Devices
Bias Resistor Transistors
PNP Silicon Surface Mount Transistors
with Monolithic Bias Resistor Network
This new series of digital transistors is designed to replace a single
device and its external resistor bias network. The BRT (Bias Resistor
Transistor) contains a single transistor with a monolithic bias network
consisting of two resistors; a series base resistor and a base-emitter
resistor. The BRT eliminates these individual components by
integrating them into a single device. The use of a BRT can reduce
both system cost and board space. The device is housed in the SOT-23
package which is designed for low power surface mount applications.
Features
• Simplifies Circuit Design
• Reduces Board Space
• Reduces Component Count
• The SOT-23 package can be soldered using wave or reflow. The
modified gull-winged leads absorb thermal stress during soldering
eliminating the possibility of damage to the die.
• Available in 8 mm embossed tape and reel.
• Pb−Free Packages are Available
MAXIMUM RATINGS (T_A = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Collector-Base Voltage
Collector-Emitter Voltage
Collector Current
THERMAL CHARACTERISTICS
V_CBO
V_CEO
I_C
50
Vdc
50
Vdc
100
mAdc
Characteristic
Symbol
Max
Unit
Total Device Dissipation
T_A = 25°C
Derate above 25°C
P_D
246 (Note 1)
mW
400 (Note 2)
1.5 (Note 1) °C/W
2.0 (Note 2)
Thermal Resistance,
Junction-to-Ambient
R_qJA
508 (Note 1)
311 (Note 2)
°C/W
Thermal Resistance,
Junction-to-Lead
R_qJL
174 (Note 1)
208 (Note 2)
°C/W
Junction and Storage,
Temperature Range
T_J, T_stg
−55 to +150
°C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. FR−4 @ Minimum Pad
2. FR−4 @ 1.0 x 1.0 inch Pad
© Semiconductor Components Industries, LLC, 2005
1
August, 2005 − Rev. 5
http://onsemi.com
PIN 1
R1
BASE
(INPUT) _R2
PIN 3
COLLECTOR
(OUTPUT)
PIN 2
EMITTER
(GROUND)
MARKING
DIAGRAM
3
1
SOT−23
CASE 318
STYLE 6
A6x M G
G
2
1
A6x = Device Code
x
= A − L (Refer to page 2)
M
= Date Code*
G
= Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation may vary depending
upon manufacturing location.
ORDERING INFORMATION
Device
MMUN21xxLT1
Package
Shipping^†
SOT−23 3000/Tape & Reel
MMUN21xxLT1G SOT−23 3000/Tape & Reel
(Pb−Free)
MMUN21xxLT3 SOT−23 10000/Tape & Reel
MMUN21xxLT3G SOT−23 10000/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
DEVICE MARKING INFORMATION
See specific marking information in the device marking table
on page 2 of this data sheet.
Preferred devices are recommended choices for future use
and best overall value.
Publication Order Number:
MMUN2111LT1/D