MC74VHC125 Datasheet, PDF (1/8 Pages) ON Semiconductor – Quad Bus Buffer

MC74VHC125
Quad Bus Buffer
with 3–State Control Inputs
The MC74VHC125 is a high speed CMOS quad bus buffer
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
The MC74VHC125 requires the 3–state control input (OE) to be set
High to place the output into the high impedance state.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7V, allowing the interface of 5V systems
to 3V systems.
• High Speed: tPD = 3.8ns (Typ) at VCC = 5V
• Low Power Dissipation: ICC = 4µA (Max) at TA = 25°C
• High Noise Immunity: VNIH = VNIL = 28% VCC
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2V to 5.5V Operating Range
• Low Noise: VOLP = 0.8V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300mA
• ESD Performance: HBM > 2000V; Machine Model > 200V
• Chip Complexity: 72 FETs or 18 Equivalent Gates
LOGIC DIAGRAM
Active–Low Output Enables
A1
2
OE1
1
5
A2
OE2
4
3
Y1
6
Y2
9
A3
OE3 ¹⁰
12
A4
OE4 ¹³
8 _Y3
11
Y4
FUNCTION TABLE
VHC125
Inputs Output
A OE Y
HL
H
LL
L
XH
Z
http://onsemi.com
14–LEAD SOIC
D SUFFIX
CASE 751A
14–LEAD TSSOP
DT SUFFIX
CASE 948G
14–LEAD SOIC EIAJ
M SUFFIX
CASE 965
PIN CONNECTION AND
MARKING DIAGRAM (Top View)
OE1 1
A1 2
Y1 3
OE2 4
A2 5
Y2 6
GND 7
14 VCC
13 OE4
12 A4
11 Y4
10 OE3
9 A3
8 Y3
For detailed package marking information, see the Marking
Diagram section on page 5 of this data sheet.
ORDERING INFORMATION
Device
Package
Shipping
MC74VHC125D
SOIC
55 Units/Rail
MC74VHC125DT TSSOP
96 Units/Rail
MC74VHC125M SOIC EIAJ 50 Units/Rail
© Semiconductor Components Industries, LLC, 2000
1
April, 2000 – Rev. 2
Publication Order Number:
MC74VHC125/D