MC74HCT373A_14 Datasheet, PDF (1/7 Pages) ON Semiconductor – Octal 3-State Noninverting Transparent Latch with LSTTL-Compatible Inputs

MC74HCT373A
Octal 3-State Noninverting
Transparent Latch with
LSTTL-Compatible Inputs
High−Performance Silicon−Gate CMOS
The MC74HCT373A may be used as a level converter for
interfacing TTL or NMOS outputs to High−Speed CMOS inputs.
The HCT373A is identical in pinout to the LS373.
The eight latches of the HCT373A are transparent D−type latches.
While the Latch Enable is high the Q outputs follow the Data Inputs.
When Latch Enable is taken low, data meeting the setup and hold
times becomes latched.
The Output Enable does not affect the state of the latch, but when
Output Enable is high, all outputs are forced to the high−impedance
state. Thus, data may be latched even when the outputs are not
enabled.
The HCT373A is identical in function to the HCT573A, which has
the input pins on the opposite side of the package from the output pins.
This device is similar in function to the HCT533A, which has
inverting outputs.
Features
• Output Drive Capability: 15 LSTTL Loads
• TTL/NMOS−Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 mA
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7 A
• Chip Complexity: 196 FETs or 49 Equivalent Gates
• These Devices are Pb−Free and are RoHS Compliant
LOGIC DIAGRAM
DATA
INPUTS
D0 ³
D1 ⁴
D2 ⁷
D3 ⁸
D4 ¹³
D5 ¹⁴
D6 ¹⁷
D7 ¹⁸
LATCH ENABLE ¹¹
OUTPUT ENABLE ¹
2 _Q0
5 _Q1
6 _Q2
9 _Q3
12 _Q4
15 _Q5
16 _Q6
19 _Q7
NONINVERTING
OUTPUTS
PIN 20 = V_CC
PIN 10 = GND
© Semiconductor Components Industries, LLC, 2014
1
September, 2014 − Rev. 13
ÎÎÎÎ
http://onsemi.com
SOIC−20
DW SUFFIX
CASE 751D
TSSOP−20
DT SUFFIX
CASE 948E
PIN ASSIGNMENT
OUTPUT
ENABLE 1
Q0 2
D0 3
D1 4
Q1 5
Q2 6
D2 7
D3 8
Q3 9
GND 10
20 VCC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 ^D4
12 ^Q4
11 LATCH
ENABLE
MARKING DIAGRAMS
20
20
HCT373A
AWLYYWWG
HCT
373A
ALYWG
G
1
1
SOIC−20
TSSOP−20
A
WL, L
YY, Y
WW, W
G or G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device
MC74HCT373ADWG
Package
SOIC−20
(Pb−Free)
Shipping^†
38 / Rail
MC74HCT373ADWR2G SOIC−20 1000 /
(Pb−Free) Tape & Reel
MC74HCT373ADTR2G TSSOP−20 2500 /
(Pb−Free) Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Publication Order Number:
MC74HCT373A/D