MC74HCT138A_15 Datasheet, PDF (1/7 Pages) ON Semiconductor – 1-of-8 Decoder/ Demultiplexer with LSTTL Compatible Inputs

MC74HCT138A
1-of-8 Decoder/
Demultiplexer with LSTTL
Compatible Inputs
High−Performance Silicon−Gate CMOS
The MC74HCT138A is identical in pinout to the LS138. The
HCT138A may be used as a level converter for interfacing TTL or
NMOS outputs to High Speed CMOS inputs.
The HCT138A decodes a three−bit Address to one−of−eight
active−lot outputs. This device features three Chip Select inputs, two
active−low and one active−high to facilitate the demultiplexing,
cascading, and chip−selecting functions. The demultiplexing function
is accomplished by using the Address inputs to select the desired
device output; one of the Chip Selects is used as a data input while the
other Chip Selects are held in their active states.
Features
• Output Drive Capability: 10 LSTTL Loads
• TTL/NMOS Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1.0 mA
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 122 FETs or 30.5 Equivalent Gates
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
LOGIC DIAGRAM
ADDRESS
INPUTS
A0 ¹
A1 ²
A2 ³
15 _Y0
14 _Y1
13 _Y2
12 _Y3
11 _Y4
10
Y5
9 _Y6
7
Y7
ACTIVE-LOW
OUTPUTS
CHIP-
CS1 ⁶
SELECT _CS2 ⁴
INPUTS
CS3
5
PIN 16 = V_CC
PIN 8 = GND
www.onsemi.com
SOIC−16
D SUFFIX
CASE 751B
TSSOP−16
DT SUFFIX
CASE 948F
PIN ASSIGNMENT
A0 1
A1 2
A2 3
CS2 4
CS3 5
CS1 6
Y7 7
GND 8
16 V_CC
15 Y0
14 _Y1
13 Y2
12 Y3
11 Y4
10 Y5
9 Y6
MARKING DIAGRAMS
16
HCT138AG
AWLYWW
1
SOIC−16
16
HCT
138A
ALYWG
G
1
TSSOP−16
A
WL, L
YY, Y
WW, W
G or G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information on page 5 of
this data sheet.
© Semiconductor Components Industries, LLC, 2015
1
June, 2015 − Rev. 11
Publication Order Number:
MC74HCT138A/D