MC74HC132A Datasheet, PDF (1/8 Pages) ON Semiconductor – Quad 2-Input NAND Gate with Schmitt-Trigger Inputs

MC74HC132A
Quad 2-Input NAND Gate
with Schmitt-Trigger Inputs
High–Performance Silicon–Gate CMOS
The MC74HC132A is identical in pinout to the LS132. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
The HC132A can be used to enhance noise immunity or to square up
slowly changing waveforms.
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 72 FETs or 18 Equivalent Gates
LOGIC DIAGRAM
A1 ¹
3
Y1
B1 ²
A2 ⁴
B2 ⁵
A3 ⁹
B3 ¹⁰
6
Y2
Y = AB
8
Y3
A4 ¹²
B4 ¹³
11
Y4
PIN 14 = VCC
PIN 7 = GND
FUNCTION TABLE
Inputs
A
B
L
L
L
H
H
L
H
H
Output
Y
H
H
H
L
http://onsemi.com
PDIP–14
N SUFFIX
CASE 646
MARKING
DIAGRAMS
14
MC74HC132AN
AWLYYWW
1
SOIC–14
D SUFFIX
CASE 751A
14
HC132A
AWLYWW
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
PIN ASSIGNMENT
A1 1
B1 2
Y1 3
A2 4
B2 5
Y2 6
GND 7
14 VCC
13 B4
12 A4
11 Y4
10 B3
9 A3
8 Y3
ORDERING INFORMATION
Device
Package Shipping
MC74HC132AN
PDIP–14 2000 / Box
MC74HC132AD
SOIC–14
55 / Rail
MC74HC132ADR2
SOIC–14 2500 / Reel
© Semiconductor Components Industries, LLC, 2000
1
March, 2000 – Rev. 7
Publication Order Number:
MC74HC132A/D