|
MC14518B Datasheet, PDF (1/8 Pages) ON Semiconductor – Dual Up Counters | |||
|
MC14518B
Dual Up Counters
The MC14518B dual BCD counter and the MC14520B dual binary
counter are constructed with MOS Pâchannel and Nâchannel
enhancement mode devices in a single monolithic structure. Each
consists of two identical, independent, internally synchronous 4âstage
counters. The counter stages are type D flipâflops, with
interchangeable Clock and Enable lines for incrementing on either the
positiveâgoing or negativeâgoing transition as required when
cascading multiple stages. Each counter can be cleared by applying a
high level on the Reset line. In addition, the MC14518B will count out
of all undefined states within two clock periods. These complementary
MOS up counters find primary use in multiâstage synchronous or
ripple counting applications requiring low power dissipation and/or
high noise immunity.
⢠Diode Protection on All Inputs
⢠Supply Voltage Range = 3.0 Vdc to 18 Vdc
⢠Internally Synchronous for High Internal and External Speeds
⢠Logic EdgeâClocked Design â Incremented on Positive Transition
of Clock or Negative Transition on Enable
⢠Capable of Driving Two Lowâpower TTL Loads or One Lowâpower
Schottky TTL Load Over the Rated Temperature Range
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Symbol
Parameter
Value
Unit
VDD
DC Supply Voltage Range
â 0.5 to +18.0
V
Vin, Vout Input or Output Voltage Range â 0.5 to VDD + 0.5
V
(DC or Transient)
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
±10
mA
PD
Power Dissipation,
per Package (Note 3.)
500
mW
TA
Operating Temperature Range
â 55 to +125
°C
Tstg
Storage Temperature Range
â 65 to +150
°C
TL
Lead Temperature
(8âSecond Soldering)
260
°C
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic âP and D/DWâ Packages: â 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
v v highâimpedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
PDIPâ16
P SUFFIX
CASE 648
MARKING
DIAGRAMS
16
MC14518BCP
AWLYYWW
1
16
SOICâ16
DW SUFFIX
CASE 751G
14518B
AWLYYWW
SOEIAJâ16
F SUFFIX
CASE 966
1
16
MC14518B
AWLYWW
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC14518BCP
MC14518BDW
PDIPâ16
SOICâ16
2000/Box
47/Rail
MC14518BDWR2 SOICâ16 1000/Tape & Reel
MC14518BF
SOEIAJâ16 See Note 1.
MC14518BFEL SOEIAJâ16 See Note 1.
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
© Semiconductor Components Industries, LLC, 2000
1
March, 2000 â Rev. 3
Publication Order Number:
MC14518B/D
|
▷ |