MC10EPT20_16 Datasheet, PDF (1/10 Pages) ON Semiconductor – LVTTL/LVCMOS to Differential LVPECL Translator

MC10EPT20, MC100EPT20
3.3 V LVTTL/LVCMOS to
Differential LVPECL
Translator
The MC10EPT20 is a 3.3 V TTL/CMOS to differential PECL
translator. Because PECL (Positive ECL) levels are used, only +3.3 V
and ground are required. The small outline SOIC−8 NB package and the
single gate of the EPT20 makes it ideal for those applications where
space, performance, and low power are at a premium.
The 100 Series contains temperature compensation.
Features
• 390 ps Typical Propagation Delay
• Maximum Input Clock Frequency > 1 GHz Typical
• Operating Range:
♦ V_CC = 3.0 V to 3.6 V with GND = 0 V
• PNP TTL Input for Minimal Loading
• Q Output will Default HIGH with Input Open
• These Devices are Pb-Free, Halogen Free and are RoHS Compliant
www.onsemi.com
8
1
SOIC−8 NB
D SUFFIX
CASE
751−07
8
1
TSSOP−8
DT SUFFIX
CASE
948R−02
DFN−8
MN SUFFIX
CASE 506AA
MARKING DIAGRAMS*
8
HPT20
ALYW
G
1
8
KPT20
ALYW
G
1
8
HA20
ALYWG
G
1
8
KA20
ALYWG
G
1
14
14
H = MC10
A
K = MC100
L
5W = MC10
Y
3Q = MC100
W
M = Date Code G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb-Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information on page 7 of
this data sheet.
© Semiconductor Components Industries, LLC, 2016
1
August, 2016 − Rev. 12
Publication Order Number:
MC10EPT20/D