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MC100LVEP111 Datasheet, PDF (1/13 Pages) ON Semiconductor – Low-Voltage 1:10 Differential LVECL/LVPECL/LVEPECL/HSTL Clock Driver | |||
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MC100LVEP111
2.5V / 3.3V 1:10 Differential
ECL/PECL/HSTL Clock Driver
Description
The MC100LVEP111 is a low skew 1âtoâ10 differential driver,
designed with clock distribution in mind, accepting two clock sources into
an input multiplexer. The PECL input signals can be either differential or
singleâended (if the VBB output is used). HSTL inputs can be used when
the LVEP111 is operating under PECL conditions.
The LVEP111 specifically guarantees low outputâtoâoutput skew.
Optimal design, layout, and processing minimize skew within a device and
from device to device.
To ensure tightest skew, both sides of differential outputs identically
terminate into 50 W even if only one output is being used. If an output
pair is unused, both outputs may be left open (unterminated) without
affecting skew.
The MC100LVEP111, as with most other ECL devices, can be
operated from a positive VCC supply in PECL mode. This allows the
LVEP111 to be used for high performance clock distribution in +3.3 V or
+2.5 V systems. Singleâended CLK input operation is limited to a VCC â¥
3.0 V in PECL mode, or VEE v â3.0 V in NECL mode when using VBB
(See Figure 10). Full operating range is available when using an external
voltage reference (See Figure 9). Designers can take advantage of the
LVEP111âs performance to distribute low skew clocks across the
backplane or the board.
Features
⢠85 ps Typical DeviceâtoâDevice Skew
⢠20 ps Typical OutputâtoâOutput Skew
⢠Jitter Less than 1 ps RMS
⢠Maximum Frequency > 3 GHz Typical
⢠VBB Output
⢠430 ps Typical Propagation Delay
⢠The 100 Series Contains Temperature Compensation
⢠PECL and HSTL Mode Operating Range: VCC = 2.375 V to 3.8 V
with VEE = 0 V
⢠NECL Mode Operating Range: VCC = 0 V
with VEE = â2.375 V to â3.8 V
⢠Open Input Default State
⢠LVDS Input Compatible
⢠Fully Compatible with MC100EP111
⢠PbâFree Packages are Available
http://onsemi.com
MARKING
DIAGRAMS*
LQFPâ32
FA SUFFIX
CASE 873A
MC100
LVEP111
AWLYYWWG
32
1
1 32
QFN32
MN SUFFIX
CASE 488AM
1
MC100
LVEP111
ALYWG
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G
= PbâFree Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
© Semiconductor Components Industries, LLC, 2008
1
December, 2008 â Rev. 17
Publication Order Number:
MC100LVEP111/D
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