CAT9554 Datasheet, PDF (1/16 Pages) Catalyst Semiconductor – Catalyst Semiconductor

CAT9554, CAT9554A
8-bit I²C and SMBus I/O Port with Interrupt
FEATURES
„ 400kHz I²C bus compatible ⁽¹⁾
„ 2.3V to 5.5V operation
„ Low stand-by current
„ 5V tolerant I/Os
„ 8 I/O pins that default to inputs at power-up
„ High drive capability
„ Individual I/O configuration
„ Polarity inversion register
„ Active low interrupt output
„ Internal power-on reset
„ No glitch on power-up
„ Noise filter on SDA/SCL inputs
„ Cascadable up to 8 devices
„ Industrial temperature range
„ RoHS-compliant 16-lead SOIC and TSSOP, and
16-pad TQFN (4 x 4mm) packages
APPLICATIONS
„ White goods (dishwashers, washing machines)
„ Handheld devices (cell phones, PDAs, digital
cameras)
„ Data Communications (routers, hubs and
servers)
BLOCK DIAGRAM ⁽¹⁾
DESCRIPTION
The CAT9554 and CAT9554A are CMOS devices that
provide 8-bit parallel input/output port expansion for
I²C and SMBus compatible applications. These I/O
expanders provide a simple solution in applications
where additional I/Os are needed: sensors, power
switches, LEDs, pushbuttons, and fans.
The CAT9554/9554A consist of an input port register,
an output port register, a configuration register, a
polarity inversion register and an I²C/SMBus-
compatible serial interface.
Any of the eight I/Os can be configured as an input or
output by writing to the configuration register. The
system master can invert the CAT9554/9554A input
data by writing to the active-high polarity inversion
register.
The CAT9554/9554A features an active low interrupt
output which indicates to the system master that an
input state has changed.
The device’s extended addressing capability allows up
to 8 devices to share the same bus. The CAT9554A is
identical to the CAT9554 except the fixed part of the
I²C slave address is different. This allows up to 16 of
devices (eight CAT9554 and eight CAT9554A) to be
connected on the same bus.
For Ordering Information details, see page 15.
A0
A1
A2
SCL
INPUT
SDA
FILTER
8-BIT
I²C/SMBUS
CONTROL
WRITE pulse
READ pulse
INPUT/
OUTPUT
PORTS
I/O₀
I/O₁
I/O₂
I/O₃
I/O₄
I/O₅
I/O₆ ^VCC
V_CC
POWER-ON
RESET
V_SS
LP FILTER
I/O₇
INT
Notes:
(1) All I/Os are set to inputs at RESET.
© 2008 SCILLC. All rights reserved
1
Characteristics subject to change without notice
Doc. No. MD-9002, Rev. F