MSC7110-01 Datasheet, PDF (8/18 Pages) OKI electronic componets – 12-Segment x 16-Digit or 16-Segment x12-Digit Display Controller/Driver

¡ Semiconductor
FEDL7110-03
MSC7110-01/7112-01
PIN DESCRIPTION
Symbol
V_DD
V_SS
V_EE
DATA IN
SCLK
LOAD
POR
OSC I
OSC O
SEGA-L
SEGA-P
D1-D12
D1-D16
LED1-LED5
Number
of Pins
1
1
1
1
1
1
Type
—
—
—
I
I
I
Connected
to
Description
Power source V_DD-V_SS: Supply voltage for internal logic
V_DD-V_EE: Supply voltage for VF display tube driving circuit
logic
Microcontroller Input of display data of the shift register
Input from the MSB (positive logic).
Shift clock of the shift register.
Data is shifted at the falling edge of SCLK.
Latch clock input for display data.
When this pin is at a "H" level, the data is not latched to pass
through the latch circuit.
When the pin is at a "L" level, the data when the pin is at the
"H" level is latched.
1
I
—
Schmitt with
pull-up
resistor
using diode
Internal logic reset input upon power-on.
During reset, the 18-bit internal latch, duty cycle register,
digital register, LED register, and write/read address
register are all reset, and the outputs of SEGA to SEGP(*a),
D1 to D12 (*b), and LED1 to LED5 go off.
Connecting of an external capacitor to the pin allows power-
on reset.
1
I
1
O
—
Input for oscillation circuit
When an external resistor and a capacitor are connected,
an oscillation circuit is formed.
C=100pF, R=47kW
f_OSC=235kHz±20%
12 *1 O Anode side of Output for driving anode electrodes of VF display tube.
16 *2
VF display tube The output is complementary.
12 2 O Grid side of VF Output for driving grid electrodes of VF display tube.
16 *1
display tube The output is complementary.
5
O
LED
LED driving output. The output is complementary.
*a SEGA to SEGL in case of MSC7110-01
*b D1 to D16 in case of MSC7110-01
*1 In case of MSC7110-01
*2 In case of MSC7112-01
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