ML60852A Datasheet, PDF (75/81 Pages) OKI electronic componets – USB Device Controller

1Semiconductor
FEDL60852A-03
ML60852A
DMA Transfer Timing (4)
ML60852A to Memory (Demand Transfer, Dual Address Mode)
Parameter
DREQ Disable Time
CS Hold Time
Read Data Delay Time
Data Hold Time
Recovery Time
Symbol
t₁
t₂
t₃
t₄
t₅
Condition
Load 20 pF
Load 20 pF
8-bit DMA
16-bit DMA
Min.
Max.
Unit
—
20
ns
0
—
ns
—
46
ns
0
—
ns
63
—
ns
105
—
ns
Notes: (1) When in Dual Address mode, the DACK is ignored.
t₃ is defined depending on CS or RD which becomes active last.
A6: A0 specifies the FIFO address.
Refer to READ Timing (1) for Address Setup Time and Address Hold Time.
(2) 3-clock time of oscillation clock (clock period: 21 ns).
(3) 5-clock time of oscillation clock (clock period: 21 ns).
Note
(1)
(2)
(3)
AD7: A0
,^D4^R-^E3^Q
+C5S
4^R,^D
DOUT
t5
t4
t3
t1
t2
Last Packet Read
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