ISP1564 Datasheet, PDF (96/99 Pages) NXP Semiconductors – Hi-Speed USB PCI host controller

NXP Semiconductors
ISP1564
HS USB PCI host controller
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Table 100.USBCMD - USB Command register bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Table 101.USBSTS - USB Status register bit allocation . .66
Table 102.USBSTS - USB Status register bit description 67
Table 103.USBINTR - USB Interrupt Enable register
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Table 104.USBINTR - USB Interrupt Enable register
bit description . . . . . . . . . . . . . . . . . . . . . . . . .69
Table 105.FRINDEX - Frame Index register
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Table 106.FRINDEX - Frame Index register
bit description . . . . . . . . . . . . . . . . . . . . . . . . .70
Table 107.N based value of FLS[1:0] . . . . . . . . . . . . . . . .70
Table 108.PERIODICLISTBASE - Periodic Frame List
Base Address register bit allocation . . . . . . . .71
Table 109.PERIODICLISTBASE - Periodic Frame List
Base Address register bit description . . . . . . .71
Table 110.ASYNCLISTADDR - Current Asynchronous
List Address register bit allocation . . . . . . . . . .71
Table 111.ASYNCLISTADDR - Current Asynchronous
List Address register bit description . . . . . . . . .72
Table 112.CONFIGFLAG - Configure Flag register
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Table 113.CONFIGFLAG - Configure Flag register
bit description . . . . . . . . . . . . . . . . . . . . . . . . .73
Table 114.PORTSC 1, 2 - Port Status and Control 1, 2
register bit allocation . . . . . . . . . . . . . . . . . . . .73
Table 115.PORTSC 1, 2 - Port Status and Control 1, 2
register bit description . . . . . . . . . . . . . . . . . . .74
Table 116.System Tuning register bit allocation . . . . . . . .76
Table 117.System Tuning register bit description . . . . . . .77
Table 118.Ring buffering disable . . . . . . . . . . . . . . . . . . .77
Table 119.Watermark disable . . . . . . . . . . . . . . . . . . . . . .77
Table 120.Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .78
Table 121.Recommended operating conditions . . . . . . . .78
Table 122.Static characteristics: I²C-bus interface
(SDA and SCL) . . . . . . . . . . . . . . . . . . . . . . . .79
Table 123.Static characteristics: digital pins
(PWE1_N, OC1_N, PWE2_N and OC2_N) . . .79
Table 124.Static characteristics: PCI interface block . . . .79
Table 125.Static characteristics: USB interface block
(pins DM1 to DM2 and DP1 to DP2) . . . . . . . .79
Table 126.Current consumption . . . . . . . . . . . . . . . . . . . .81
Table 127.Current consumption: S1 and S3 . . . . . . . . . . .81
Table 128.Dynamic characteristics: system clock timing .82
Table 129.Dynamic characteristics: I²C-bus interface
(SDA and SCL) . . . . . . . . . . . . . . . . . . . . . . . .82
Table 130.Dynamic characteristics: PCI interface block . .82
Table 131.Dynamic characteristics: high-speed source
electrical characteristics . . . . . . . . . . . . . . . . .82
Table 132.Dynamic characteristics: full-speed source
electrical characteristics . . . . . . . . . . . . . . . . .83
Table 133.Dynamic characteristics: low-speed source
electrical characteristics . . . . . . . . . . . . . . . . .83
Table 134.PCI clock and I/O timing . . . . . . . . . . . . . . . . .84
Table 135.SnPb eutectic process (from J-STD-020C) . . .89
Table 136.Lead-free process (from J-STD-020C) . . . . . .89
Table 137.Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 138.Revision history . . . . . . . . . . . . . . . . . . . . . . . . 91
ISP1564_2
Product data sheet
Rev. 02 — 13 November 2008
© NXP B.V. 2008. All rights reserved.
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