ISP1564 Datasheet, PDF (12/99 Pages) NXP Semiconductors – Hi-Speed USB PCI host controller

NXP Semiconductors
ISP1564
HS USB PCI host controller
7.7 Power-On Reset (POR)
Figure 4 shows a possible curve of V_I(VAUX3V3) and V_I(VREG3V3) with dips at t2 to t3 and
t4 to t5. At t0, POR will start with 1. At t1, the detector passes through the trip level.
Another delay will be added before POR drops to 0 to ensure that the length of the
generated detector pulse, POR, is large enough to reset asynchronous flip-flops. If the dip
is too short (t4 to t5 < 11 µs), POR will not react and will stay LOW.
t0
t1
t2
t3
V_POR(trip) is typically 0.9 V.
Fig 4. Power-on reset
V_I(VAUX3V3), V_I(VREG3V3)
V_POR(trip)
t4 t5
POR
004aab194
7.8 Power supply
Figure 5 shows the ISP1564 power supply connection.
ISP1564_2
Product data sheet
Rev. 02 — 13 November 2008
© NXP B.V. 2008. All rights reserved.
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