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SSTUA32866 Datasheet, PDF (9/28 Pages) NXP Semiconductors – 1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-667 RDIMM applications
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NXP Semiconductors
SSTUA32866
1.8 V DDR2-667 configurable registered buffer with parity
7.1 Function table
Table 3. Function table (each flip-flop)
L = LOW voltage level; H = HIGH voltage level; X = don’t care; ↑ = LOW-to-HIGH transition; ↓ = HIGH-to-LOW transition
Inputs
Outputs[1]
RESET
DCS
CSR
CK
CK
Dn, DODTn, Qn
DCKEn
QCS
QODT,
QCKE
H
L
L
↑
↓
L
L
L
L
H
L
L
↑
↓
H
H
L
H
H
L
H
L
L
L or H
L or H
X
Q0
Q0
Q0
H
↑
↓
L
L
L
L
H
L
H
↑
↓
H
H
L
H
H
L
H
H
H
L or H
L or H
X
Q0
Q0
Q0
L
↑
↓
L
L
H
L
H
H
L
↑
↓
H
H
H
H
H
H
H
H
H
H
L
L or H
L or H
X
Q0
Q0
Q0
H
↑
↓
L
Q0
H
L
H
↑
↓
H
Q0
H
H
H
H
H
L or H
L or H
X
Q0
Q0
Q0
L
X or floating X or floating X or floating X or floating X or floating
L
L
L
[1] Q0 is the previous state of the associated output.
Table 4. Parity and standby function table
L = LOW voltage level; H = HIGH voltage level; X = don’t care; ↑ = LOW-to-HIGH transition; ↓ = HIGH-to-LOW transition
Inputs
Outputs[1]
RESET
DCS
CSR
CK
CK
∑ of inputs = H PAR_IN[2] PPO[3] QERR[4]
(D1 to D25)
H
L
X
↑
↓
even
L
L
H
H
L
X
↑
↓
odd
L
H
L
H
L
X
↑
↓
even
H
H
L
H
L
X
↑
↓
odd
H
L
H
H
H
L
↑
↓
even
L
L
H
H
H
L
↑
↓
odd
L
H
L
H
H
L
↑
↓
even
H
H
L
H
H
L
↑
↓
odd
H
L
H
H
H
H
↑
↓
X
X
PPO0 QERR0
H
X
X
L or H
L or H
X
X
PPO0 QERR0
L
X or floating X or floating X or floating X or floating X or floating X or floating
L
H
[1] PPO0 is the previous state of output PPO; QERR0 is the previous state of output QERR.
[2] Data inputs = D2, D3, D5, D6, D8 to D25 when C0 = 0 and C1 = 0.
Data inputs = D2, D3, D5, D6, D8 to D14 when C0 = 0 and C1 = 1.
Data inputs = D1 to D6, D8 to D10, D12, D13 when C0 = 1 and C1 = 1.
[3] PAR_IN arrives one clock cycle (C0 = 0), or two clock cycles (C0 = 1), after the data to which it applies.
[4] This condition assumes QERR is HIGH at the crossing of CK going HIGH and CK going LOW. If QERR is LOW, it stays latched LOW for
two clock cycles or until RESET is driven LOW.
SSTUA32866_2
Product data sheet
Rev. 02 — 26 March 2007
© NXP B.V. 2007. All rights reserved.
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