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| SSTUA32866 Datasheet, PDF (15/28 Pages) NXP Semiconductors – 1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-667 RDIMM applications | |||
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NXP Semiconductors
SSTUA32866
1.8 V DDR2-667 conï¬gurable registered buffer with parity
RESET
DCS
CSR
CK
m
m+1
m+2
m+3
m+4
CK
tsu
th
D1
to
D14
tPD
CK to Q
Q1
to
Q14
tsu th
PAR_IN(1)
PPO
(not used)
QERR
tPD
CK to PPO
tPD
CK to QERR
tPD
CK to QERR
002aaa657
(1) PAR_IN is driven from PPO of the ï¬rst SSTUA32866 device.
Fig 9. Timing diagram for the second SSTUA32866 (1 : 2 Register B conï¬guration) device used in pair;
C0 = 1, C1 = 1
SSTUA32866_2
Product data sheet
Rev. 02 â 26 March 2007
© NXP B.V. 2007. All rights reserved.
15 of 28
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