SC18IS600 Datasheet, PDF (9/30 Pages) NXP Semiconductors – SPI to IC-bus interface

NXP Semiconductors
SC18IS600/601
SPI to I²C-bus interface
V_DD
P
strong
pin latch data
input data
Fig 9. Push-pull output configuration
N
V_SS
GPIO pin
glitch rejection
002aab885
6.2.2 I/O pins state register (IOState)
When read, this register returns the actual state of all programmable and
quasi-bidirectional I/O pins. When written, each register bit will be transferred to the
corresponding I/O pin programmed as output.
Table 5.
Bit
7:6
5
4
3
2
1
0
IOState - I/O pins state register (address 0x01) bit description
Symbol
Description
-
reserved
IO5
Set the logic level on the output pins.
IO4
GPIO3 (SC18IS600 only)
GPIO2
GPIO1
Write to this register:
logic 0 = set output pin to zero
logic 1 = set output pin to one
A read from this register returns states of all pins.
GPIO0
6.2.3 I²C-bus address register (I2CAdr)
The contents of the register represents the device’s own I²C-bus address. The most
significant bit corresponds to the first bit received from the I²C-bus after a START
condition. The least significant bit is not used, but should be programmed with a ‘0’.
I2CAdr is not needed for device operation, but should be configured so that its address
does not conflict with an I²C-bus device address used by the bus master.
6.2.4 I²C-bus clock rates register (I2CClk)
This register determines the I²C-bus clock frequency. Various clock rates are shown in
Table 6 for the SC18IS600. The frequency can be determined using Equation 1:
I²C-bus clock frequency = ⁷--₄-^.--³-_×--⁷---^2I---₂₈---_C-^×---_C--¹---_l0--_k-⁶- (Hz)
(1)
SC18IS600_601_5
Product data sheet
Rev. 05 — 28 July 2008
© NXP B.V. 2008. All rights reserved.
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