PCA9535A Datasheet, PDF (9/38 Pages) NXP Semiconductors – Low-voltage 16-bit I2C-bus I/O port with interrupt

NXP Semiconductors
PCA9535A
Low-voltage 16-bit I²C-bus I/O port with interrupt
6.4 Power-on reset
When power (from 0 V) is applied to V_DD, an internal power-on reset holds the PCA9535A
in a reset condition until V_DD has reached V_POR. At that time, the reset condition is
released and the PCA9535A registers and I²C-bus/SMBus state machine initializes to
their default states. After that, V_DD must be lowered to below V_PORF and back up to the
operating voltage for a power-reset cycle. See Section 8.2 “Power-on reset requirements”.
6.5 Interrupt output
An interrupt is generated by any rising or falling edge of the port inputs in the Input mode.
After time t_v(INT), the signal INT is valid. The interrupt is reset when data on the port
changes back to the original value or when data is read form the port that generated the
interrupt (see Figure 10 and Figure 11). Resetting occurs in the Read mode at the
acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL
signal. Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very
short) due to the resetting of the interrupt during this pulse. Any change of the I/Os after
resetting is detected and is transmitted as INT.
A pin configured as an output cannot cause an interrupt. Changing an I/O from an output
to an input may cause a false interrupt to occur, if the state of the pin does not match the
contents of the Input Port register.
7. Bus transactions
The PCA9535A is an I²C-bus slave device. Data is exchanged between the master and
PCA9535A through write and read commands using I²C-bus. The two communication
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
7.1 Writing to the port registers
Data is transmitted to the PCA9535A by sending the device address and setting the least
significant bit to a logic 0 (see Figure 4 “PCA9535A device address”). The command byte
is sent after the address and determines which register will receive the data following the
command byte.
Eight registers within the PCA9535A are configured to operate as four register pairs. The
four pairs are input port, output port, polarity inversion, configuration registers. After
sending data to one register, the next data byte is sent to the other register in the pair (see
Figure 7 and Figure 8). For example, if the first byte is sent to Output Port 1 (register 3),
the next byte is stored in Output Port 0 (register 2).
There is no limitation on the number of data bytes sent in one write transmission. In this
way, the host can continuously update a register pair independently of the other registers,
or the host can simply update a single register.
PCA9535A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 11 September 2012
© NXP B.V. 2012. All rights reserved.
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