PCA9535A Datasheet, PDF (13/38 Pages) NXP Semiconductors – Low-voltage 16-bit I2C-bus I/O port with interrupt

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data into port 0
data into port 1
DATA 00
t_h(D)
DATA 10
DATA 01
INT
t_v(INT)
t_rst(INT)
SCL 1 2 3 4 5 6 7 8 9
R/W
slave address
I0.x
SDA S 0 1 0 0 A2 A1 A0 1 A
DATA 00
A
START condition
read from port 0
acknowledge
from slave
acknowledge
from master
read from port 1
DATA 02
t_su(D)
t_h(D)
DATA 11
I1.x
DATA 10
A
acknowledge
from master
DATA 03
t_su(D)
I0.x
DATA 03
A
acknowledge
from master
DATA 12
I1.x
STOP condition
DATA 12
1P
non acknowledge
from master
002aah376
Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It
is assumed that the command byte has previously been set to ‘00’ (read input port register).
This figure eliminates the command byte transfer and a restart between the initial slave address call and the actual data transfer from P port (see Figure 9).
Fig 11. Read input port register, scenario 2