DAC1008D750 Datasheet, PDF (86/99 Pages) NXP Semiconductors – Dual 10-bit DAC up to 750 Msps 2×, 4× or 8× interpolating with JESD204A interface

NXP Semiconductors
DAC1008D750
2×, 4× or 8× interpolating with JESD204A
10.15.2.14 Page 7 bit definition detailed description
Please refer to Table 173 for a register overview and their default values. In the following
tables, all the values emphasized in bold are the default values.
Table 174. LN2_CFG_0 register (address 00h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value
7 to 0 LN2_DID[7:0]
R
-
Description
lane 2 device ID
Table 175. LN2_CFG_1 register (address 01h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value
3 to 0 LN2_BID[3:0]
R
-
Description
lane 2 bank ID
Table 176. LN2_CFG_2 register (address 02h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value
4 to 0 LN2_LID[4:0]
R
-
Description
lane 2 lane ID
Table 177. LN2_CFG_3 register (address 03h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value
7
LN2_SCR
R
-
4 to 0 LN2_L[4:0]
R
-
Description
scrambling on
number of lanes minus 1
Table 178. LN2_CFG_4 register (address 04h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value
7 to 0 LN2_F[7:0]
R
-
Description
number of octets per frame minus 1
Table 179. LN2_CFG_5 register (address 05h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value
4 to 0 LN2_K[4:0]
R
-
Description
number of frames per multiframe minus 1
Table 180. LN2_CFG_6 register (address 06h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value
7 to 0 LN2_M[7:0]
R
-
Description
number of converters per device minus 1
Table 181. LN2_CFG_7 register (address 07h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value
7 to 6 LN2_CS[1:0]
R
-
4 to 0 LN2_N[4:0]
R
-
Description
number of control bits
converter resolution minus 1
DAC1008D750_1
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 4 October 2010
© NXP B.V. 2010. All rights reserved.
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