SC16C850V Datasheet, PDF (8/47 Pages) NXP Semiconductors – 1.8 V single UART, 5 Mbit/s (max.) with 128-byte FIFOs, infrared (IrDA), and XScale VLIO bus interface

NXP Semiconductors
SC16C850V
Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
[3] Second special registers are accessible only when EFCR[0] = 1.
[4] Enhanced Feature Registers are only accessible when LCR = 0xBF.
[5] First extra feature registers are only accessible when EFCR[2:1] = 01b.
[6] Second extra feature registers are only accessible when EFCR[2:1] = 10b.
6.4 FIFO operation
6.4.1 32-byte FIFO mode
When all four of these registers (TXINTLVL, RXINTLVL, FLWCNTH, FLWCNTL) in the
First Extra Register Set are empty (0x00) the transmit and receive trigger levels are set by
FCR[7:4]. In this mode the transmit and receive trigger levels are backward compatible to
the SC16C650B (see Table 5), and the FIFO sizes are 32 entries. The transmit and
receive data FIFOs are enabled by the FIFO Control Register bit 0 (FCR[0]). It should be
noted that the user can set the transmit trigger levels by writing to the FCR, but activation
will not take place until EFR[4] is set to a logic 1. The receiver FIFO section includes a
time-out function to ensure data is delivered to the external CPU (see Section 6.8). Please
refer to Table 10 and Table 11 for the setting of FCR[7:4].
Table 5. Interrupt trigger level and Flow control mechanism
FCR[7:6]
FCR[5:4]
INT pin activation
RX
TX
Negate RTS or
send Xoff
00
00
8
16
8
01
01
16
8
16
10
10
24
24
24
11
11
28
30
28
Assert RTS
or send Xon
0
7
15
23
6.4.2 128-byte FIFO mode
When either TXINTLVL, RXINTLVL, FLWCNTH or FLWCNTL in the First Extra Register
Set contains any value other than 0x00, the transmit and receive trigger levels are set by
TXINTLVL and RXINTLVL registers. TXINTLVL sets the trigger levels for the transmit
FIFO, and the transmit trigger levels can be set to any value between 1 and 128 with
granularity of 1. RXINTLVL sets the trigger levels for the receive FIFO, the receive trigger
levels can be set to any value between 1 and 128 with granularity of 1.
When the effective FIFO size changes (that is, when FCR[0] toggles or when the
combined content of TXINTLVL, RXINTLVL, FLWCNTH and FLWCNTL changes between
equal and unequal to 0x00), both RX FIFO and TX FIFO will be reset (data in the FIFO will
be lost).
6.5 Hardware flow control
When automatic hardware flow control is enabled, the SC16C850V monitors the CTS pin
for a remote buffer overflow indication and controls the RTS pin for local buffer overflows.
Automatic hardware flow control is selected by setting EFR[6] (RTS) and EFR[7] (CTS) to
a logic 1. If CTS transitions from a logic 0 to a logic 1 indicating a flow control request,
ISR[5] will be set to a logic 1 (if enabled via IER[7:6]), and the SC16C850V will suspend
TX transmissions as soon as the stop bit of the character in process is shifted out.
Transmission is resumed after the CTS input returns to a logic 0, indicating more data may
be sent.
SC16C850V_4
Product data sheet
Rev. 04 — 14 January 2008
© NXP B.V. 2008. All rights reserved.
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