74HC273-Q100 Datasheet, PDF (8/19 Pages) NXP Semiconductors – Octal D-type flip-flop with reset; positive-edge trigger

NXP Semiconductors
74HC273-Q100; 74HCT273-Q100
Octal D-type flip-flop with reset; positive-edge trigger
Table 7. Dynamic characteristics …continued
GND (ground = 0 V); C_L = 50 pF unless otherwise specified; for test circuit, see Figure 10
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max
Min
Max
t_PHL
HIGH to LOW MR to Qn; see Figure 8
propagation
delay
V_CC = 2.0 V
V_CC = 4.5 V
- 44 150 -
185
-
- 16 30
-
37
-
225 ns
45 ns
V_CC = 5.0 V; C_L = 15 pF
- 15 -
-
-
-
- ns
V_CC = 6.0 V
- 14 26
-
31
-
38 ns
t_t
transition time Qn output; see Figure 7 ^[2]
V_CC = 2.0 V
- 19 75
-
95
-
110 ns
V_CC = 4.5 V
- 7 15
-
19
-
22 ns
V_CC = 6.0 V
- 6 13
-
15
-
19 ns
t_W
pulse width
CP input HIGH or LOW;
see Figure 7
V_CC = 2.0 V
V_CC = 4.5 V
V_CC = 6.0 V
MR input LOW;
see Figure 8
80 14 - 100
-
120
- ns
16 5 -
20
-
24
- ns
14 4 -
17
-
20
- ns
V_CC = 2.0 V
60 17 -
75
-
90
- ns
V_CC = 4.5 V
12 6 -
15
-
18
- ns
V_CC = 6.0 V
10 5 -
13
-
15
- ns
t_rec
recovery time MR to CP; see Figure 8
V_CC = 2.0 V
50 6 -
65
-
75
- ns
V_CC = 4.5 V
10 2 -
13
-
15
- ns
V_CC = 6.0 V
9 2 -
11
-
13
- ns
t_su
set-up time
Dn to CP; see Figure 9
V_CC = 2.0 V
60 11 -
75
-
90
- ns
V_CC = 4.5 V
12 4 -
15
-
18
- ns
V_CC = 6.0 V
10 3 -
13
-
15
- ns
t_h
hold time
Dn to CP; see Figure 9
V_CC = 2.0 V
3 6 -
3
-
3
- ns
V_CC = 4.5 V
3 2 -
3
-
3
- ns
V_CC = 6.0 V
3 2 -
3
-
3
- ns
f_max
maximum
frequency
CP input; see Figure 7
V_CC = 2.0 V
6 20.6 -
4.8
-
4
- MHz
V_CC = 4.5 V
30 103 -
24
-
20
- MHz
V_CC = 5.0 V; C_L = 15 pF
- 66 -
-
-
-
- MHz
V_CC = 6.0 V
35 122 -
28
-
24
- MHz
C_PD
power
per package;
dissipation
V_I = GND to V_CC
capacitance
[3] _{- 20 -}
-
-
-
- pF
74HC_HCT273_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 19 June 2013
© NXP B.V. 2013. All rights reserved.
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