P89V664FA512 Datasheet, PDF (79/90 Pages) NXP Semiconductors – 8-bit 80C51 5 V low power 16 kB/32 kB/64 kB flash microcontroller with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI

NXP Semiconductors
P89V660/662/664
80C51 with 512 B/1 kB/2 kB RAM, dual I²C-bus, SPI
SCL
(input/
output)
SDA
(input/
output)
START or repeated START condition
t_rDA
t_fDA
t_rCL
t_fCL
t_HD;STA t_LOW
t_HIGH
t_SU;DAT
Fig 41. I²C-bus interface timing
t_HD;DAT
repeated START condition
STOP condition
t_SU;STA
t_BUF
t_SU;STO
0.7V_CC
0.3V_CC
t_suDAT2
t_suDAT1
START
condition
0.7V_CC
0.3V_CC
002aab861
Table 75. SPI interface timing
Symbol Parameter
Conditions
f_SPI
T_SPICYC
t_SPILEAD
t_SPILAG
t_SPICLKH
t_SPICLKL
t_SPIDSU
t_SPIDH
t_SPIA
t_SPIDIS
t_SPIDV
t_SPIOH
t_SPIR
t_SPIF
SPI operating frequency
SPI cycle time
SPI enable lead time
SPI enable lag time
SPICLK HIGH time
SPICLK LOW time
SPI data set-up time
SPI data hold time
SPI access time
SPI disable time
SPI enable to output
data valid time
SPI output data hold
time
SPI rise time
SPI outputs (SPICLK,
MOSI, MISO)
SPI inputs (SPICLK,
MOSI, MISO, SS)
SPI fall time
SPI outputs (SPICLK,
MOSI, MISO)
SPI inputs (SPICLK,
MOSI, MISO, SS)
see Figure 42, 43, 44, 45
see Figure 44, 45
see Figure 44, 45
see Figure 42, 43, 44, 45
see Figure 42, 43, 44, 45
master or slave; see
Figure 42, 43, 44, 45
master or slave; see
Figure 42, 43, 44, 45
see Figure 44, 45
see Figure 44, 45
see Figure 42, 43, 44, 45
see Figure 42, 43, 44, 45
see Figure 42, 43, 44, 45
see Figure 42, 43, 44, 45
Variable clock
Min
Max
0
4T_cy(clk)
250
T_cy(clk) / 4
-
-
250
-
2T_cy(clk)
-
2T_cy(clk)
-
100
-
100
-
0
80
0
160
-
111
0
-
f_osc = 18 MHz Unit
Min Max
0
10 MHz
222
- ns
250
- ns
250
- ns
111
- ns
111
- ns
100
- ns
100
- ns
0
80 ns
-
160 ns
-
111 ns
0
- ns
-
100
-
100 ns
-
2000
- 2000 ns
-
100
-
100 ns
-
2000
- 2000 ns
P89V660_662_664
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3.1 — 17 October 2011
© NXP B.V. 2011. All rights reserved.
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