PCA9544A_09 Datasheet, PDF (7/26 Pages) NXP Semiconductors – 4-channel I2C-bus multiplexer with interrupt logic

NXP Semiconductors
PCA9544A
4-channel I²C-bus multiplexer with interrupt logic
Table 4. Control register: Write—channel selection; Read—channel status
INT3 INT2 INT1 INT0 D3 B2 B1 B0 Command
X
X
X
X
X
0
X
x
no channel selected
X
X
X
X
X
1
0
0
channel 0 enabled
X
X
X
X
X
1
0
1
channel 1 enabled
X
X
X
X
X
1
1
0
channel 2 enabled
X
X
X
0
X
1
1
1
channel 3 enabled
0
0
0
0
0
0
0
0
no channel selected;
power-up default state
6.3 Interrupt handling
The PCA9544A provides 4 interrupt inputs, one for each channel and one open-drain
interrupt output. When an interrupt is generated by any device, it will be detected by the
PCA9544A and the interrupt output will be driven LOW. The channel need not be active
for detection of the interrupt. A bit is also set in the control byte. Bits 7:4 of the control byte
correspond to channel 3 to channel 0 of the PCA9544A, respectively. Therefore, if an
interrupt is generated by any device connected to channel 2, the state of the interrupt
inputs is loaded into the control register when a read is accomplished. Likewise, an
interrupt on any device connected to channel 0 would cause bit 4 of the control register to
be set on the read. The master can then address the PCA9544A and read the contents of
the control byte to determine which channel contains the device generating the interrupt.
The master can then reconfigure the PCA9544A to select this channel, and locate the
device generating the interrupt and clear it. The interrupt clears when the device
originating the interrupt clears.
It should be noted that more than one device can be providing an interrupt on a channel,
so it is up to the master to ensure that all devices on a channel are interrogated for an
interrupt.
The interrupt inputs may be used as general purpose inputs if the interrupt function is not
required.
If unused, interrupt input(s) must be connected to V_DD through a pull-up resistor.
Table 5. Control register read — interrupt
INT3 INT2 INT1 INT0 D3 B2 B1 B0 Command
0
no interrupt on channel 0
X
X
X
X
X
X
X
1
interrupt on channel 0
0
no interrupt on channel 1
X
X
X
X
X
X
X
1
interrupt on channel 1
0
no interrupt on channel 2
X
X
X
X
X
X
X
1
interrupt on channel 2
0
no interrupt on channel 3
X
X
X
X
X
X
X
1
interrupt on channel 3
Remark: Several interrupts can be active at the same time. For example: INT3 = 0,
INT2 = 1, INT1 = 1, INT0 = 0, means that there is no interrupt on channel 0 and
channel 3, and there is an interrupt on channel 1 and on channel 2.
PCA9544A_4
Product data sheet
Rev. 04 — 15 June 2009
© NXP B.V. 2009. All rights reserved.
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