ADC1004S030 Datasheet, PDF (7/19 Pages) NXP Semiconductors – Single 10 bits ADC, up to 30 MHz, 40 MHz or 50 MHz

NXP Semiconductors
ADC1004S030/040/050
Single 10 bits ADC, up to 30 MHz, 40 MHz or 50 MHz
Table 6. Characteristics …continued
V_CCA = V3 to V4 = 4.75 V to 5.25 V; V_CCD = V11 to V12 and V28 to V27 = 4.75 V to 5.25 V;
V_CCO = V13 to V14 = 3.0 V to 5.25 V; AGND and DGND shorted together; T_amb = 0 °C to +70 °C; typical values measured at
V_CCA = V_CCD = 5 V and V_CCO = 3.3 V; C_L = 15 pF and T_amb = 25 °C; unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
R_lad
TC_Rlad
ladder resistance
ladder resistor temperature
coefficient
-
245
-
Ω
-
456
-
mΩ/K
V_offset
V_i(a)(p-p)
offset voltage
peak-to-peak analog input
voltage
BOTTOM;
V_RT − V_RB = 2.37
TOP;
V_RT − V_RB = 2.37
[2] _-
[2] _-
[3] _1.7
175
-
mV
175
-
mV
2.02
2.55
V
Digital outputs D9 to D0 and IR (referenced to OGND)
V_OL
LOW-level output voltage I_OL = 1 mA
V_OH
HIGH-level output voltage I_OH = −1 mA
I_O
output current
in 3-state mode;
0.5 V < V_O < V_CCO
Switching characteristics; Clock input CLK; see Figure 4^[1]
0
-
V_CCO − 0.5 -
−20
-
0.5
V
V_CCO
V
+20
µA
f_clk(max) maximum clock frequency ADC1004S030TS
30
-
-
ADC1004S040TS
40
-
-
MHz
MHz
ADC1004S050TS
50
-
-
MHz
t_w(clk)H
HIGH clock pulse width
full effective
bandwidth
8.5
-
-
ns
t_w(clk)L
LOW clock pulse width
full effective
bandwidth
5.5
-
-
ns
Analog signal processing
Linearity
INL
integral non-linearity
f_clk = 40 MHz;
ramp input
-
±0.8
±2.0
LSB
DNL
differential non-linearity
f_clk = 40 MHz;
ramp input
-
±0.5
±0.9
LSB
E_offset
offset error
E_G
gain error
Bandwidth (f_clk = 40 MHz)
B
bandwidth
middle code;
-
V_RB = 1.3 V;
V_RT = 3.67 V
from device to device; ^[4] -
V_RB = 1.3 V;
V_RT = 3.67 V
full-scale sine wave
[5] _-
±1
-
±0.1
-
15
-
LSB
%
MHz
75 % full-scale sine
-
wave
20
-
MHz
small signal at
-
mid-scale;
V_I = ±10 LSB at code
512
350
-
MHz
ADC1004S030_040_050_3
Product data sheet
Rev. 03 — 7 August 2008
© NXP B.V. 2008. All rights reserved.
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