LPC1850 Datasheet, PDF (65/84 Pages) NXP Semiconductors – 32-bit ARM Cortex-M3 MCU; up to 200 kB SRAM; Ethernet, two High-speed USB, LCD

NXP Semiconductors
LPC1850/30/20/10
32-bit ARM Cortex-M3 microcontroller
SCK (CPOL = 0)
SCK (CPOL = 1)
MOSI
MISO
T_cy(clk)
t_clk(H)
t_clk(L)
t_v(Q)
DATA VALID
DATA VALID
DATA VALID
t_DS
t_DH
DATA VALID
t_h(Q)
CPHA = 1
MOSI
MISO
t_v(Q)
DATA VALID
DATA VALID
DATA VALID
t_DS
t_DH
DATA VALID
t_h(Q)
Fig 19. SSP master timing in SPI mode
CPHA = 0
002aae829
LPC1850_30_20_10
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 3 January 2011
© NXP B.V. 2011. All rights reserved.
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